Tools/Xilinx ISE/DCM

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(Created page with "{{TOC right}} In order to divide the clock frequency, a [http://www.xilinx.com/products/intellectual-property/dcm_module.html Digital Clock manager] (DCM) module can be insta...")
 
(Saprtan 6)
 
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module can be instantiated.
 
module can be instantiated.
  
= Instanciation =
+
= Instantiation =
 +
 
 +
== Saprtan 3 ==
 +
 
 +
In a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Spartan-3] FPGA, the associated module is a <code>DCM_SP</code>.
 +
 
 +
Here a sample code:
 +
library UNISIM;
 +
  use UNISIM.vcomponents.all;
 +
 
 +
  I_DCM: dcm_clkgen
 +
    generic map (
 +
      clkfx_multiply    => 3,
 +
      clkfx_divide      => 8,
 +
      clkin_period      => 10.0
 +
    )
 +
    port map (
 +
      rst      => '0',
 +
      clkin    => clockIn,
 +
      clkfx    => clock
 +
    );
 +
 
 +
The <code>library</code> definition and its associated <code>use</code> clause must:
 +
* be in the code for compilation
 +
* be commented-out for HDL Designer to generate the concatenated file (else further simulation VHDL code is included and will not be accepted at synthesis)
 +
* be de-commented for synthesis (which is done in our <code>trimlibs.pl</code>)
 +
 
 +
Additionally, the <code>hdp</code> preferences file must specify a definition in the HDS section for the unisim library:
 +
<pre>
 +
[ModelSim]
 +
unisim = $ISE_HOME/ISE/vhdl/unisim/work
 +
[hdl]
 +
unisim = $ISE_HOME/../../vhdl/src/unisims
 +
[hds]
 +
unisim = $HDS_PROJECT_DIR/../unisim/hds
 +
</pre>
 +
 
 +
If it isn't the case, the HDL Designer vhdl file generator will produce:
 +
<pre>
 +
Error: Cross reference directory '' cannot be written to. Generation cannot proceed.
 +
Please make sure this directory is write enabled.
 +
</pre>
  
 
== Saprtan 6 ==
 
== Saprtan 6 ==

Latest revision as of 15:22, 10 August 2015

Contents

In order to divide the clock frequency, a Digital Clock manager (DCM) module can be instantiated.

Instantiation

Saprtan 3

In a Spartan-3 FPGA, the associated module is a DCM_SP.

Here a sample code:

library UNISIM;
  use UNISIM.vcomponents.all;
 
  I_DCM: dcm_clkgen
    generic map (
      clkfx_multiply    => 3,
      clkfx_divide      => 8,
      clkin_period      => 10.0
    )
    port map (
      rst       => '0',
      clkin     => clockIn,
      clkfx     => clock
    );

The library definition and its associated use clause must:

  • be in the code for compilation
  • be commented-out for HDL Designer to generate the concatenated file (else further simulation VHDL code is included and will not be accepted at synthesis)
  • be de-commented for synthesis (which is done in our trimlibs.pl)

Additionally, the hdp preferences file must specify a definition in the HDS section for the unisim library:

[ModelSim]
unisim = $ISE_HOME/ISE/vhdl/unisim/work
[hdl]
unisim = $ISE_HOME/../../vhdl/src/unisims
[hds]
unisim = $HDS_PROJECT_DIR/../unisim/hds

If it isn't the case, the HDL Designer vhdl file generator will produce:

Error: Cross reference directory '' cannot be written to. Generation cannot proceed.
Please make sure this directory is write enabled.

Saprtan 6

In a Spartan-6 FPGA, the associated module is a DCM_SP or a DCM_CLKGEN.

Here a sample code:

library UNISIM;
  use UNISIM.vcomponents.all;
 
  I_DCM: dcm_clkgen
    generic map (
      clkfx_multiply    => 3,
      clkfx_divide      => 8,
      clkin_period      => 10.0
    )
    port map (
      rst       => '0',
      freezedcm => '0',
      clkin     => clockIn,
      clkfx     => clock
    );

UniSim library

Adding the UniSim to the HDS tool can be done with:

unisim = $ISE_HOME/ISE/vhdl/src/unisims


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