https://wiki.hevs.ch/chessobc/index.php5?title=OBC/PIC_PIC_microcontroller&feed=atom&action=historyOBC/PIC PIC microcontroller - Revision history2024-03-29T10:58:39ZRevision history for this page on the wikiMediaWiki 1.18.1https://wiki.hevs.ch/chessobc/index.php5?title=OBC/PIC_PIC_microcontroller&diff=9&oldid=prevFrancois.corthay: Created page with "=PIC18LF26K83= ==Configuration== Clock is set to the highest value (64MHz) as the board is made for test purposes. It could be lowered if a such speed is not needed for the fi..."2020-09-18T10:01:46Z<p>Created page with "=PIC18LF26K83= ==Configuration== Clock is set to the highest value (64MHz) as the board is made for test purposes. It could be lowered if a such speed is not needed for the fi..."</p>
<p><b>New page</b></p><div>=PIC18LF26K83=<br />
==Configuration==<br />
Clock is set to the highest value (64MHz) as the board is made for test purposes. It could be lowered if a such speed is not needed for the final use. Typically in order to reduce power consumption<br />
<br />
Note that if done so, some parameters may need to be changed<br />
===CAN===<br />
As described in the ADCS control document, the CAN configuration is the following :<br />
version 2.0 B, extended ID, SP set to 87.5% and SJW = 1, bus speed 125 kbps.<br />
<br />
{|class=wikitable<br />
|-<br />
! Register || Hex || Parameter || Description<br />
|-<br />
|rowspan="2"| BRGCON1<br />
|rowspan="2"| 0x0F<br />
| BRP || (2x16)/FOSC<br />
|-<br />
| SJW || 1 x TQ<br />
|-<br />
|rowspan="4"| BRGCON2<br />
|rowspan="4"| 0xBC<br />
| PRSEG || 5 x TQ<br />
|-<br />
| SAM || once at sample point<br />
|-<br />
| SEG1PH || 8 x TQ<br />
|-<br />
| SEG2PHTS || Freely programmable<br />
|-<br />
|rowspan="3"| BRGCON3<br />
|rowspan="3"| 0x01<br />
| SEG2PH || 2 x TQ<br />
|-<br />
| WAKDIS || Enable CAN wake-up<br />
|-<br />
| WAKFIL || CAN line filter not used<br />
|-<br />
|}<br />
<br />
===UART===<br />
<br />
===SPI===<br />
<br />
===ADC===</div>Francois.corthay