https://wiki.hevs.ch/ete/api.php5?action=feedcontributions&user=Francois.corthay&feedformat=atomETE - User contributions [en]2024-03-28T18:39:36ZUser contributionsMediaWiki 1.18.1https://wiki.hevs.ch/ete/index.php5/Tools/EDA/InstallTools/EDA/Install2022-12-07T13:39:24Z<p>Francois.corthay: /* Linux */</p>
<hr />
<div>{{TOC right}}<br />
<br />
= ModelSim =<br />
<br />
ModelSim is used to simulate digital circuits.<br />
<br />
== Windows ==<br />
<br />
Download installer to local PC:<br />
{{TaskBox|content=<br />
Get the installer from <code>R:\ETE\Ele1_8132\ELN\Software\VHDL\ModelSim\modelsim-win64-10.4f-se.exe</code>.}}<br />
<br />
Install:<br />
{{TaskBox|content=<br />
Set following options during the installation process:<br />
* Target location: <code>C:\eda\MentorGraphics\ModelSim</code>}}<br />
<br />
== Linux ==<br />
=== Download Modelsim ===<br />
<br />
The following files need to be downloaded from <code>R:\ETE\Ele1_8132\ELN\Software\VHDL\ModelSim\</code>.<br />
* install.linux<br />
* modelsim-base.mis | questasim-base.mis<br />
* modelsim-docs.mis | questasim-docs.mis<br />
* modelsim-linux_<version>.mis | questasim-linux_<version>.mis<br />
<br />
=== Set executable rights ===<br />
<br />
<source lang="Bash"><br />
chmod +x install.linux<br />
</source><br />
<br />
=== Execute installer ===<br />
<br />
<source lang="Bash"><br />
sudo ./install.linux<br />
</source><br />
Install at <code>/usr/opt/Modelsim</code>.<br />
<br />
= HDL-Designer =<br />
<br />
HDL-Designer is used to design digital circuits.<br />
<br />
== Windows ==<br />
<br />
Download installer to local PC:<br />
{{TaskBox|content=<br />
Get the installer from <code>R:\ETE\Ele1_8132\ELN\Software\VHDL\HDL-Designer\HDS_2019.2_win.exe</code>.<br />
and launch it.}}<br />
<br />
Install:<br />
{{TaskBox|content=<br />
Set following options during the installation process:<br />
* Target location: <code>C:\eda\MentorGraphics\HDS\</code><br />
* Product selection: <code>HDL Designer</code><br />
* no dongle installation}}<br />
<br />
== Linux ==<br />
<br />
This setup is done for Ubuntu<br />
<br />
{{TaskBox|content=<br />
For '''x86-64''' systems, install 32 bit libraries:<br />
<source lang='bash'><br />
sudo apt install ia32-libs<br />
</source><br />
<br />
For '''mulitarch''' systems (typically Ubuntu 12.04 or newer), install <br />
<source lang='bash'><br />
sudo apt install libxi6:i386 libXp6:i386 libXmu6:i386<br />
</source><br />
}}<br />
<br />
{{TaskBox|content=<br />
Copy the installer from <code>R:\ETE\Ele1_8132\ELN\Software\VHDL\HDL-Designer\HDS_2015.2_ixl.exe</code> to <code>/home/<i>user</i>/Downloads/EDA</code><br />
}}<br />
<br />
{{TaskBox|content=<br />
Install it:<br />
<source lang='bash'><br />
cd /home/<i>user</i>/Downloads/EDA/<br />
chmod +x HDS_*.exe<br />
sudo ./HDS_*.exe<br />
</source><br />
<br />
Options:<br />
* Target location: <code>/usr/opt/HDS</code><br />
* Product selection: HDL Designer<br />
}}<br />
<br />
= License =<br />
== Windows ==<br />
<br />
{{WarningBox|content=<br />
To be able to get a license you have to be connected to the school network either way directly by cable, through the school wifi ''secure-hevs'' or through VPN.}}<br />
<br />
{{TaskBox|content=<br />
Add the license server location to your computers environment variables:<br />
* right-click on <code>Computer -> Properties -> Advanced -> Environment Variables</code><br />
* select or add a new <code>LM_LICENSE_FILE</code> variable<br />
* add <code>27001@mentorlm.hevs.ch</code><br />
}}<br />
<br />
== Linux ==<br />
<br />
<br />
{{TaskBox|content=<br />
Add path and license server info:<br />
<source lang='bash'><br />
export PATH=$PATH:/usr/opt/HDS/bin<br />
export LM_LICENSE_FILE=$LM_LICENSE_FILE:27001@mentorlm.hevs.ch<br />
</source><br />
}}<br />
<br />
{{TaskBox|content=<br />
Test the application:<br />
<source lang='bash'><br />
cd /tmp/<br />
hdl_designer &<br />
</source><br />
}}<br />
<br />
{{TaskBox|content=<br />
Update the settings:<br />
<source lang='bash'><br />
sudo nano -w /etc/profile<br />
</source><br />
}}<br />
<br />
= ISE =<br />
<br />
Extract <code>ISE_DS-12.1.tar</code> to a temporary folder on the desktop.<br />
<br />
Launch <code>xsetup</code> to install it.<br />
Options:<br />
* Edition to install: Logic Edition<br />
* Installation Options: Acquire or manage a license key + Install Cable Drivers<br />
* Destination Directory: <code>C:\EDA\Xilinx</code><br />
* Don't import tool preferences from previous version<br />
<br />
Add license server info:<br />
* right-click on my computer -> Properties -> Advanced -> Environment Variables<br />
* select <code>LM_LICENSE_FILE</code><br />
* add <code>;2100@xilinxlm.hevs.ch</code></div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Tools/EDA/InstallTools/EDA/Install2022-12-07T13:38:35Z<p>Francois.corthay: /* Linux */</p>
<hr />
<div>{{TOC right}}<br />
<br />
= ModelSim =<br />
<br />
ModelSim is used to simulate digital circuits.<br />
<br />
== Windows ==<br />
<br />
Download installer to local PC:<br />
{{TaskBox|content=<br />
Get the installer from <code>R:\ETE\Ele1_8132\ELN\Software\VHDL\ModelSim\modelsim-win64-10.4f-se.exe</code>.}}<br />
<br />
Install:<br />
{{TaskBox|content=<br />
Set following options during the installation process:<br />
* Target location: <code>C:\eda\MentorGraphics\ModelSim</code>}}<br />
<br />
== Linux ==<br />
=== Download Modelsim ===<br />
<br />
The following files need to be downloaded from <code>R:\ETE\Ele1_8132\ELN\Software\VHDL\ModelSim\</code>.<br />
* install.linux<br />
* modelsim-base.mis | questasim-base.mis<br />
* modelsim-docs.mis | questasim-docs.mis<br />
* modelsim-linux_<version>.mis | questasim-linux_<version>.mis<br />
<br />
=== Set executable rights ===<br />
<br />
<source lang="Bash"><br />
chmod +x install.linux<br />
</source><br />
<br />
=== Execute installer ===<br />
<br />
<source lang="Bash"><br />
sudo ./install.linux<br />
</source><br />
Install at <code>/usr/opt/Modelsim</code>.<br />
<br />
= HDL-Designer =<br />
<br />
HDL-Designer is used to design digital circuits.<br />
<br />
== Windows ==<br />
<br />
Download installer to local PC:<br />
{{TaskBox|content=<br />
Get the installer from <code>R:\ETE\Ele1_8132\ELN\Software\VHDL\HDL-Designer\HDS_2019.2_win.exe</code>.<br />
and launch it.}}<br />
<br />
Install:<br />
{{TaskBox|content=<br />
Set following options during the installation process:<br />
* Target location: <code>C:\eda\MentorGraphics\HDS\</code><br />
* Product selection: <code>HDL Designer</code><br />
* no dongle installation}}<br />
<br />
== Linux ==<br />
<br />
This setup is done for Ubuntu<br />
<br />
{{TaskBox|content=<br />
For '''x86-64''' systems, install 32 bit libraries:<br />
<source lang='bash'><br />
sudo apt install ia32-libs<br />
</source><br />
<br />
For '''mulitarch''' systems (typically Ubuntu 12.04 or newer), install <br />
<source lang='bash'><br />
sudo apt install libxi6:i386 libXp6:i386 libXmu6:i386<br />
</source><br />
}}<br />
<br />
{{TaskBox|content=<br />
Copy the installer from <code>R:\ETE\Ele1_8132\ELN\Software\VHDL\HDL-Designer\HDS_2015.2_ixl.exe</code> to <code>/home/<i>user</i>/Downloads/EDA</code><br />
}}<br />
<br />
{{TaskBox|content=<br />
Install it:<br />
<source lang='bash'><br />
cd /home/<i>user</i>/Downloads/EDA/<br />
chmod +x HDS_*.exe<br />
sudo ./HDS_*.exe<br />
</source><br />
<br />
Options:<br />
* Target location: <code>/usr/opt/HDS</code><br />
* Product selection: HDL Designer<br />
}}<br />
<br />
= License =<br />
== Windows ==<br />
<br />
{{WarningBox|content=<br />
To be able to get a license you have to be connected to the school network either way directly by cable, through the school wifi ''secure-hevs'' or through VPN.}}<br />
<br />
{{TaskBox|content=<br />
Add the license server location to your computers environment variables:<br />
* right-click on <code>Computer -> Properties -> Advanced -> Environment Variables</code><br />
* select or add a new <code>LM_LICENSE_FILE</code> variable<br />
* add <code>27001@mentorlm.hevs.ch</code><br />
}}<br />
<br />
== Linux ==<br />
<br />
<br />
{{TaskBox|content=<br />
Add path and license server info:<br />
<source lang='bash'><br />
export PATH=$PATH:/usr/opt/HDS/bin<br />
export LM_LICENSE_FILE=$LM_LICENSE_FILE:27001@mentorlm.hevs.ch<br />
</source><br />
}}<br />
<br />
{{TaskBox|content=<br />
Test the application:<br />
<source lang='bash'><br />
cd /tmp/<br />
hdl_designer &<br />
</source><br />
}}<br />
<br />
{{TaskBox|content=<br />
Update the settings:<br />
<source lang='bash'><br />
sudo nano -w /etc/profile<br />
</source><br />
<br />
= ISE =<br />
<br />
Extract <code>ISE_DS-12.1.tar</code> to a temporary folder on the desktop.<br />
<br />
Launch <code>xsetup</code> to install it.<br />
Options:<br />
* Edition to install: Logic Edition<br />
* Installation Options: Acquire or manage a license key + Install Cable Drivers<br />
* Destination Directory: <code>C:\EDA\Xilinx</code><br />
* Don't import tool preferences from previous version<br />
<br />
Add license server info:<br />
* right-click on my computer -> Properties -> Advanced -> Environment Variables<br />
* select <code>LM_LICENSE_FILE</code><br />
* add <code>;2100@xilinxlm.hevs.ch</code><br />
<br />
Add the lines:<br />
#------------------------------------------------------------------------------- <br />
# EDA tools<br />
#<br />
export PATH=$PATH:/usr/opt/HDS/bin<br />
export LM_LICENSE_FILE=$LM_LICENSE_FILE:27001@mentorlm.hevs.ch<br />
}}</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE_labs/presentations/COMEln/ETE labs/presentations/COM2022-11-25T10:54:04Z<p>Francois.corthay: /* Shift register */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
This lab presents:<br />
* the serial port<br />
* the design of Finite State Machines (FSM)<br />
<br />
= System =<br />
<br />
The testbench comprises a sender and a receiver.<br />
The students are asked to develop the sender. '''The receiver is optional'''.<br />
<br />
The serial signal looks like:<br />
[[File:ElN serial transmission.svg|750 px|center]]<br />
<br />
In order to decode it we need:<br />
* a shift register<br />
* a counter to cope with the baudrate<br />
* a Finite State Machine (FSM) to control the system<br />
<br />
The receiver is shown in the folloowing figure. The sender has serial and parallel exchanged.<br />
[[File:Eln labs serial receiver.svg|300 px|center]]<br />
<br />
The number of bis of the counter has to be chosen by the students and specified in the declaration section.<br />
<br />
= Drawing state machines =<br />
<br />
Open the FSM and show:<br />
* reset and clock<br />
* adding states<br />
* drawing arrows: show priorities, explain remaining in the state<br />
* assignment to the outputs (with the default values)<br />
<br />
= Design =<br />
<br />
== Shift register ==<br />
<br />
The shift register needs E-flipflops.<br />
The sender also needs multiplexers in order to select loading a value or shifting the bits.<br />
<br />
Additionally to the 8 bits :<br />
* The very first FF receives '1' during shifting for the stop bits.<br />
* A supplemental FF at the end of the shift register loads a '0' for the start bit. This FF has an asynchronous preset for the power-on stop bit.<br />
<br />
= Update =<br />
<br />
Use the same shift register for the sender and the receiver ?</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE_labs/presentations/COMEln/ETE labs/presentations/COM2022-11-25T10:53:54Z<p>Francois.corthay: /* Shift register */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
This lab presents:<br />
* the serial port<br />
* the design of Finite State Machines (FSM)<br />
<br />
= System =<br />
<br />
The testbench comprises a sender and a receiver.<br />
The students are asked to develop the sender. '''The receiver is optional'''.<br />
<br />
The serial signal looks like:<br />
[[File:ElN serial transmission.svg|750 px|center]]<br />
<br />
In order to decode it we need:<br />
* a shift register<br />
* a counter to cope with the baudrate<br />
* a Finite State Machine (FSM) to control the system<br />
<br />
The receiver is shown in the folloowing figure. The sender has serial and parallel exchanged.<br />
[[File:Eln labs serial receiver.svg|300 px|center]]<br />
<br />
The number of bis of the counter has to be chosen by the students and specified in the declaration section.<br />
<br />
= Drawing state machines =<br />
<br />
Open the FSM and show:<br />
* reset and clock<br />
* adding states<br />
* drawing arrows: show priorities, explain remaining in the state<br />
* assignment to the outputs (with the default values)<br />
<br />
= Design =<br />
<br />
== Shift register ==<br />
<br />
The shift register needs E-flipflops.<br />
The sender also needs multiplexers in order to select loading a value or shifting the bits.<br />
Additionally to the 8 bits :<br />
* The very first FF receives '1' during shifting for the stop bits.<br />
* A supplemental FF at the end of the shift register loads a '0' for the start bit. This FF has an asynchronous preset for the power-on stop bit.<br />
<br />
= Update =<br />
<br />
Use the same shift register for the sender and the receiver ?</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE_labs/presentations/COMEln/ETE labs/presentations/COM2022-11-25T10:52:01Z<p>Francois.corthay: /* Update */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
This lab presents:<br />
* the serial port<br />
* the design of Finite State Machines (FSM)<br />
<br />
= System =<br />
<br />
The testbench comprises a sender and a receiver.<br />
The students are asked to develop the sender. '''The receiver is optional'''.<br />
<br />
The serial signal looks like:<br />
[[File:ElN serial transmission.svg|750 px|center]]<br />
<br />
In order to decode it we need:<br />
* a shift register<br />
* a counter to cope with the baudrate<br />
* a Finite State Machine (FSM) to control the system<br />
<br />
The receiver is shown in the folloowing figure. The sender has serial and parallel exchanged.<br />
[[File:Eln labs serial receiver.svg|300 px|center]]<br />
<br />
The number of bis of the counter has to be chosen by the students and specified in the declaration section.<br />
<br />
= Drawing state machines =<br />
<br />
Open the FSM and show:<br />
* reset and clock<br />
* adding states<br />
* drawing arrows: show priorities, explain remaining in the state<br />
* assignment to the outputs (with the default values)<br />
<br />
= Design =<br />
<br />
== Shift register ==<br />
<br />
The shift register needs E-flipflops.<br />
The sender also needs multiplexers in order to select loading a value or shifting the bits.<br />
The very first FF receives '1' during shifting for the stop bits.<br />
A supplemental FF at the end of the shift register loads a '0' for the start bit.<br />
<br />
= Update =<br />
<br />
Use the same shift register for the sender and the receiver ?</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE_labs/presentations/COMEln/ETE labs/presentations/COM2022-11-25T10:07:59Z<p>Francois.corthay: /* Shift register */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
This lab presents:<br />
* the serial port<br />
* the design of Finite State Machines (FSM)<br />
<br />
= System =<br />
<br />
The testbench comprises a sender and a receiver.<br />
The students are asked to develop the sender. '''The receiver is optional'''.<br />
<br />
The serial signal looks like:<br />
[[File:ElN serial transmission.svg|750 px|center]]<br />
<br />
In order to decode it we need:<br />
* a shift register<br />
* a counter to cope with the baudrate<br />
* a Finite State Machine (FSM) to control the system<br />
<br />
The receiver is shown in the folloowing figure. The sender has serial and parallel exchanged.<br />
[[File:Eln labs serial receiver.svg|300 px|center]]<br />
<br />
The number of bis of the counter has to be chosen by the students and specified in the declaration section.<br />
<br />
= Drawing state machines =<br />
<br />
Open the FSM and show:<br />
* reset and clock<br />
* adding states<br />
* drawing arrows: show priorities, explain remaining in the state<br />
* assignment to the outputs (with the default values)<br />
<br />
= Design =<br />
<br />
== Shift register ==<br />
<br />
The shift register needs E-flipflops.<br />
The sender also needs multiplexers in order to select loading a value or shifting the bits.<br />
The very first FF receives '1' during shifting for the stop bits.<br />
A supplemental FF at the end of the shift register loads a '0' for the start bit.<br />
<br />
= Update =<br />
<br />
Use the same shift register for the sender and the receiver.</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE_labs/presentations/COMEln/ETE labs/presentations/COM2022-11-25T10:07:19Z<p>Francois.corthay: /* Drawing state machines */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
This lab presents:<br />
* the serial port<br />
* the design of Finite State Machines (FSM)<br />
<br />
= System =<br />
<br />
The testbench comprises a sender and a receiver.<br />
The students are asked to develop the sender. '''The receiver is optional'''.<br />
<br />
The serial signal looks like:<br />
[[File:ElN serial transmission.svg|750 px|center]]<br />
<br />
In order to decode it we need:<br />
* a shift register<br />
* a counter to cope with the baudrate<br />
* a Finite State Machine (FSM) to control the system<br />
<br />
The receiver is shown in the folloowing figure. The sender has serial and parallel exchanged.<br />
[[File:Eln labs serial receiver.svg|300 px|center]]<br />
<br />
The number of bis of the counter has to be chosen by the students and specified in the declaration section.<br />
<br />
= Drawing state machines =<br />
<br />
Open the FSM and show:<br />
* reset and clock<br />
* adding states<br />
* drawing arrows: show priorities, explain remaining in the state<br />
* assignment to the outputs (with the default values)<br />
<br />
= Design =<br />
<br />
== Shift register ==<br />
<br />
The shift register needs E-flipflops.<br />
The sender also needs multiplexers in order to select loading a value or shifting the bits.<br />
The very first FF receives '1' during shifting for the stop bits.<br />
A supplemental FF at the end of the shift register loads a '0' for the start bit.</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE_labs/presentations/COMEln/ETE labs/presentations/COM2022-11-25T08:56:36Z<p>Francois.corthay: /* System */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
This lab presents:<br />
* the serial port<br />
* the design of Finite State Machines (FSM)<br />
<br />
= System =<br />
<br />
The testbench comprises a sender and a receiver.<br />
The students are asked to develop the sender. '''The receiver is optional'''.<br />
<br />
The serial signal looks like:<br />
[[File:ElN serial transmission.svg|750 px|center]]<br />
<br />
In order to decode it we need:<br />
* a shift register<br />
* a counter to cope with the baudrate<br />
* a Finite State Machine (FSM) to control the system<br />
<br />
The receiver is shown in the folloowing figure. The sender has serial and parallel exchanged.<br />
[[File:Eln labs serial receiver.svg|300 px|center]]<br />
<br />
The number of bis of the counter has to be chosen by the students and specified in the declaration section.<br />
<br />
= Drawing state machines =<br />
<br />
Open the FSM and show:<br />
* reset and clock<br />
* adding states<br />
* drawing arrows: show priorities, explain remaining in the state<br />
* assignment to the outputs (with the default values)</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/File:Eln_labs_serial_receiver.svgFile:Eln labs serial receiver.svg2022-11-25T08:51:04Z<p>Francois.corthay: </p>
<hr />
<div></div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/File:ElN_serial_transmission.svgFile:ElN serial transmission.svg2022-11-25T08:47:51Z<p>Francois.corthay: </p>
<hr />
<div></div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Synchro/board_combinationSynchro/board combination2022-10-26T10:23:03Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! Synchro board<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Power<br/>cable || Ribbon cable<br/>long/short<br />
! Group<br />Members || Comment<br />
|- <br />
| ETE-1 || 01 || 21 || 1 || 11 || yes || v || 1/1 || || with serial port<br />
|- <br />
| ETE-2 || 02 || 12 || 2 || 12 || yes || v || 1/1 || ||<br />
|- <br />
| ETE-3 || 03 || 13 || 3 || 13 || yes || v || 1/1 || || scan chain not seen<br />
|- <br />
| ETE-4 || 04 || 14 || 4 || 14 || yes || v || 1/1 || ||<br />
|- <br />
| ETE-5 || 05 || 15 || 5 || 15 || yes || v || 1/1 || || <br />
|- <br />
| ETE-6 || 06 || 16 || 6 || 16 || yes || v || 1/1 || ||<br />
|- <br />
| ETE-7 || 07 || 17 || 9 || 17 || yes || v || 1/1 || ||<br />
|- <br />
| ETE-8 || 08 || 22 || 8 || 18 || yes || v || 1/1 || || with serial port<br />
<!--<br />
|- <br />
| ETE-9 || 16 || 19 || 99 || 9 || no || x || 0/1 || ||<br />
|- <br />
| ETE-10 || 17 || 20 || 95 || 10 || no || x || 0/1 || ||<br />
|- <br />
| ETE-11 || 70 || 21 || 96 || 11 || no || x || 1/1 || ||<br />
|- <br />
| ETE-12 || 12 || 22 || 97 || 12 || no || x || 1/1 || ||<br />
|- <br />
| ETE-13 || 13 || 23 || 98 || 13 || no || x || 1/1 || ||<br />
|- <br />
| ETE-14 || 14 || 24 || 99 || 14 || no || x || 1/1 || ||<br />
--><br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Synchro]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Synchro/board_combinationSynchro/board combination2022-10-14T15:21:25Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! Synchro board<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Power<br/>cable || Ribbon cable<br/>long/short<br />
! Group<br />Members || Comment<br />
|- <br />
| ETE-1 || 01 || 21 || 1 || 11 || no || x || 1/1 || || with serial port<br />
|- <br />
| ETE-2 || 02 || 12 || 2 || 12 || no || x || 1/1 || ||<br />
|- <br />
| ETE-3 || 03 || 13 || 3 || 13 || no || x || 1/1 || || scan chain not seen<br />
|- <br />
| ETE-4 || 04 || 14 || 4 || 14 || no || x || 1/1 || ||<br />
|- <br />
| ETE-5 || 05 || 15 || 5 || 15 || no || x || 1/1 || || <br />
|- <br />
| ETE-6 || 06 || 16 || 6 || 16 || no || x || 1/1 || ||<br />
|- <br />
| ETE-7 || 07 || 17 || 9 || 17 || no || x || 1/1 || ||<br />
|- <br />
| ETE-8 || 08 || 22 || 8 || 18 || no || x || 1/1 || || with serial port<br />
<!--<br />
|- <br />
| ETE-9 || 16 || 19 || 99 || 9 || no || x || 0/1 || ||<br />
|- <br />
| ETE-10 || 17 || 20 || 95 || 10 || no || x || 0/1 || ||<br />
|- <br />
| ETE-11 || 70 || 21 || 96 || 11 || no || x || 1/1 || ||<br />
|- <br />
| ETE-12 || 12 || 22 || 97 || 12 || no || x || 1/1 || ||<br />
|- <br />
| ETE-13 || 13 || 23 || 98 || 13 || no || x || 1/1 || ||<br />
|- <br />
| ETE-14 || 14 || 24 || 99 || 14 || no || x || 1/1 || ||<br />
--><br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Synchro]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE_labs/presentations/PHAEln/ETE labs/presentations/PHA2022-09-27T06:25:55Z<p>Francois.corthay: /* Modelsim */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
= General presentation =<br />
<br />
* course objectives<br />
** provide the basics of digital electronics<br />
* lab objectives<br />
** build the know-how to develop a complete digital system in the project at the semester end<br />
** get acquainted to the EDA tools<br />
** discover 0/1 for the numbers<br />
** discover 0/1 for false/true<br />
* course of the laboratory work<br />
** a word on numbers<br />
** a word on logic gates<br />
** don't hesitate to ask questions<br />
* groups<br />
* labs, grades<br />
* report<br />
** Cyberlearn : how to write a lab report<br />
** reports are presented at the beginning of the following lab, group for group, in PDF form<br />
<br />
* Lab support files<br />
** download zip<br />
** keep such as both have a copy<br />
<br />
= Lab presentation =<br />
<br />
* synchronization of a generator<br />
* 4-LED display<br />
* read the lab specification<br />
<br />
= HDL Designer =<br />
<br />
* gates<br />
* wires /connection by name<br />
<br />
* page setup<br />
* printing<br />
<br />
= Modelsim =<br />
<br />
* testbench<br />
* compilation<br />
** on TB, no subblock selected<br />
** on icon through-components selected<br />
* do-file (read, save)<br />
* add a signal in the waveforms panel<br />
* time scale</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-12-22T08:33:24Z<p>Francois.corthay: /* H-bridge */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter H-bridge board]<br />
is powered with 12&nbsp;V.<br />
The 4&nbsp;[https://www.micro-semiconductor.nz/datasheet/0d-IRF7809.pdf IRF7809] MOS transistors are driven by 2&nbsp;[https://www.infineon.com/dgdl/Infineon-IR2110-DataSheet-v01_00-EN.pdf?fileId=5546d462533600a4015355c80333167e IR2113S] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch must be greater then 200&nbsp;ns.<br />
<br />
In order for the dead time effect to be negligible, the PWM period will be chosen to be in the order of magnitude off 100&nbsp;times longer thant the dead time itself.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to a 5&nbsp;V regulator and from there to a connector.<br />
From this connector, a cable is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals<br />
in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is close to 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes can be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
The PWM modes are further explained in the following sections:<br />
* [[Inverter/laboratoires|Travaux de laboratoire]]<br />
* [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-12-22T06:55:18Z<p>Francois.corthay: /* Getting started */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter H-bridge board]<br />
is powered with 12&nbsp;V.<br />
The 4&nbsp;[https://www.micro-semiconductor.nz/datasheet/0d-IRF7809.pdf IRF7809] MOS transistors are driven by 2&nbsp;[https://www.infineon.com/dgdl/Infineon-IR2110-DataSheet-v01_00-EN.pdf?fileId=5546d462533600a4015355c80333167e IR2113S] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch must be greater then 50&nbsp;ns.<br />
<br />
In order for the dead time effect to be negligible, the PWM period will be chosen to be in the order of magnitude off 100&nbsp;times longer thant the dead time itself.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to a 5&nbsp;V regulator and from there to a connector.<br />
From this connector, a cable is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals<br />
in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is close to 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes can be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
The PWM modes are further explained in the following sections:<br />
* [[Inverter/laboratoires|Travaux de laboratoire]]<br />
* [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-12-22T06:53:14Z<p>Francois.corthay: /* PWM modes */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter H-bridge board]<br />
is powered with 12&nbsp;V.<br />
The 4&nbsp;[https://www.micro-semiconductor.nz/datasheet/0d-IRF7809.pdf IRF7809] MOS transistors are driven by 2&nbsp;[https://www.infineon.com/dgdl/Infineon-IR2110-DataSheet-v01_00-EN.pdf?fileId=5546d462533600a4015355c80333167e IR2113S] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch must be greater then 50&nbsp;ns.<br />
<br />
In order for the dead time effect to be negligible, the PWM period will be chosen to be in the order of magnitude off 100&nbsp;times longer thant the dead time itself.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to a 5&nbsp;V regulator and from there to a connector.<br />
From this connector, a cable is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals<br />
in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is close to 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-12-22T06:51:47Z<p>Francois.corthay: /* H-bridge */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter H-bridge board]<br />
is powered with 12&nbsp;V.<br />
The 4&nbsp;[https://www.micro-semiconductor.nz/datasheet/0d-IRF7809.pdf IRF7809] MOS transistors are driven by 2&nbsp;[https://www.infineon.com/dgdl/Infineon-IR2110-DataSheet-v01_00-EN.pdf?fileId=5546d462533600a4015355c80333167e IR2113S] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch must be greater then 50&nbsp;ns.<br />
<br />
In order for the dead time effect to be negligible, the PWM period will be chosen to be in the order of magnitude off 100&nbsp;times longer thant the dead time itself.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to a 5&nbsp;V regulator and from there to a connector.<br />
From this connector, a cable is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals<br />
in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is close to 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-12-10T11:35:12Z<p>Francois.corthay: /* Components */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter H-bridge board]<br />
is powered with 12&nbsp;V.<br />
The 4&nbsp;[https://www.micro-semiconductor.nz/datasheet/0d-IRF7809.pdf IRF7809] MOS transistors are driven by 2&nbsp;[https://www.infineon.com/dgdl/Infineon-IR2110-DataSheet-v01_00-EN.pdf?fileId=5546d462533600a4015355c80333167e IR2113S] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch is of about 50&nbsp;ns.<br />
<br />
In order for the dead time effect to be negligible, the PWM period will be chosen to be in the order of magnitude off 1000&nbsp;times longer thant the dead time itself.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to a 5&nbsp;V regulator and from there to a connector.<br />
From this connector, a cable is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals<br />
in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is close to 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/File:Inverter_system.svgFile:Inverter system.svg2021-12-10T11:20:05Z<p>Francois.corthay: uploaded a new version of &quot;File:Inverter system.svg&quot;</p>
<hr />
<div>inverter projet system view</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-12-06T15:22:49Z<p>Francois.corthay: /* H-bridge */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The H-bridge board is powered with 12&nbsp;V.<br />
The 4&nbsp;[https://www.micro-semiconductor.nz/datasheet/0d-IRF7809.pdf IRF7809] MOS transistors are driven by 2&nbsp;driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch is of about 50&nbsp;ns.<br />
<br />
In order for the dead time effect to be negligible, the PWM period will be chosen to be in the order of magnitude off 1000&nbsp;times longer thant the dead time itself.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to a 5&nbsp;V regulator and from there to a connector.<br />
From this connector, a cable is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is something like 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-12-06T15:04:05Z<p>Francois.corthay: /* H-bridge */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The H-bridge board is powered with 12&nbsp;V.<br />
The 4&nbsp;[https://www.micro-semiconductor.nz/datasheet/0d-IRF7809.pdf IRF7809] MOS transistors are driven by 2¬nbsp;driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch is of about 50&nbsp;ns.<br />
<br />
In order for the dead time effect to be negligible, the PWM period will be chosen to be in the order of magnitude off 1000&nbsp;times longer thant the dead time.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to a 5&nbsp;V regulator and from there to a connector.<br />
From this connector, a cable is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is something like 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-12-06T15:03:27Z<p>Francois.corthay: /* H-bridge */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The H-bridge board is powered with 12&nbsp;V.<br />
The 4&nbsp;[https://www.micro-semiconductor.nz/datasheet/0d-IRF7809.pdf IRF7809]MOS transistors are driven by 2¬nbsp;driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch is of about 50&nbsp;ns.<br />
<br />
In order for the dead time effect to be negligible, the PWM period will be chosen to be in the order of magnitude off 1000&nbsp;times longer thant the dead time.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to a 5&nbsp;V regulator and from there to a connector.<br />
From this connector, a cable is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is something like 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-12-03T12:23:40Z<p>Francois.corthay: /* H-bridge */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The H-bridge board is powered with 12&nbsp;V.<br />
The 4&nbsp;MOS transistors are driven by 2&nbsp;[https://www.micro-semiconductor.nz/datasheet/0d-IRF7809.pdf IRF7809] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch is of about 50&nbsp;ns.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to the ribbon cable connector and is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is something like 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-11-26T14:22:20Z<p>Francois.corthay: /* Inverter board */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The H-bridge board is powered with 12&nbsp;V.<br />
The 4&nbsp;MOS transistors are driven by 2&nbsp;[http://www.irf.com/product-info/datasheets/data/ir2110.pdf IR2110] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch is of about 50&nbsp;ns.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to the ribbon cable connector and is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is something like 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-11-26T14:21:35Z<p>Francois.corthay: /* = LC lowpass */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The H-bridge board is powered with 12&nbsp;V.<br />
The 4&nbsp;MOS transistors are driven by 2&nbsp;[http://www.irf.com/product-info/datasheets/data/ir2110.pdf IR2110] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch is of about 50&nbsp;ns.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to the ribbon cable connector and is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ====<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is something like 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-11-26T14:21:20Z<p>Francois.corthay: /* Components */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA board]<br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_inverter inverter board]<br />
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board]<br />
<br />
=== FPGA board ===<br />
<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Inverter board ===<br />
<br />
==== H-bridge ====<br />
The H-bridge board is powered with 12&nbsp;V.<br />
The 4&nbsp;MOS transistors are driven by 2&nbsp;[http://www.irf.com/product-info/datasheets/data/ir2110.pdf IR2110] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch is of about 50&nbsp;ns.<br />
The PWM controls are brought to the inverter board via a ribbon cable.<br />
<br />
The 12&nbsp;V power supply from this board is brought to the ribbon cable connector and is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
==== LC lowpass ===<br />
The LC lowpass is used in conjunction with the H-bridge.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The LC cutoff frequency is something like 100&nbsp;Hz.<br />
<br />
==== Transformer ====<br />
The transformer allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 12&nbsp;V to xxx&nbsp;V (TBD).<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
<br />
==== Logic-level LC lowpass ====<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
For this lowpass, the default LC cutoff frequency is something like 20&nbsp;kHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/InverterInverter2021-11-26T07:05:47Z<p>Francois.corthay: /* Function */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://www.hevs.ch/ete Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Power_inverter inverter] project is to generate a 50&nbsp;Hz AC power supply from a DC input.<br />
<br />
[[File:Inverter 110 V generator setup.JPG|500px|center]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The 12&nbsp;V power supply is chopped by the power switches of an [https://en.wikipedia.org/wiki/H_bridge H-bridge] in order to generate a sine wave.<br />
The resulting voltage is filtered by a passive LC filter to provide a smooth sine wave.<br />
The digital system generates the PWM controls of the 4&nbsp;power switches.<br />
<br />
[[File:Inverter system.svg|500px|center]]<br />
<br />
An I/O board with 4&nbsp;switches and 8&nbsp;LEDs allows to control the operating mode and to display information about the system's state.<br />
<br />
=== PWM modes ===<br />
<br />
Different PWM modes are to be investigated:<br />
* a two-level mode with inverted controls on each H-bridge branch<br />
* three-level modes with separate controls on each branch<br />
<br />
=== Output ===<br />
<br />
The system has to generate a 110&nbsp;VAC power supply.<br />
<br />
This is achieved with the help of a transformer.<br />
This transformer:<br />
* provides ah high enough voltage amplitude to allow the generation of a 110&nbsp;VAC output from a 12&nbsp;power supply<br />
* transforms a differential signal into a floating one, allowing a simple measurement.<br />
<br />
As the output voltage is high, '''great care has to be taken''' with the transformer output side.<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [[Inverter#H-bridge power board|H-bridge power board]] together with a [[Inverter#Power LC lowpass board|power LC lowpass board]]<br />
* a [[Inverter#Transformer board|transformer board]]<br />
* an [[Inverter#FPGA_board|FPGA prototyping board]]<br />
* an [[Inverter#Buttons and LEDs I/O board|buttons and LEDs I/O board]] for the control<br />
* a [[Inverter#Logic-level LC lowpass board|logic-level LC lowpass board]]<br />
<br />
=== H-bridge power board ===<br />
The H-bridge board is powered with 12&nbsp;V.<br />
The 4&nbsp;MOS transistors are driven by 2&nbsp;[http://www.irf.com/product-info/datasheets/data/ir2110.pdf IR2110] driver circuits.<br />
The dead time between the switching of the upper and lower part of an H-bridge branch is of about 500&nbsp;ns.<br />
The PWM controls are brought to the board via a ribbon cable.<br />
<br />
This board is also used for an [http://wiki.hevs.ch/fsi/index.php5/EMVs/AudioAmp audio amplifier] student project.<br />
<br />
The 12&nbsp;V power supply from this board is brought to the ribbon cable connector and is used to power the [[Inverter#FPGA_board|FPGA board]] as well.<br />
<br />
=== Power LC lowpass board ===<br />
The LC lowpass board is used in conjunction with the H-bridge power board.<br />
It smooths the PWM signal into a sine wave.<br />
<br />
The default LC cutoff frequency is something like 20&nbsp;kHz, as this board is also used for an audio amplifier.<br />
<br />
=== Transformer board ===<br />
The transformer board allows to reference the differential output to any common voltage.<br />
<br />
The board at our disposal transforms 7.5&nbsp;V to 115&nbsp;V.<br />
As it provides a high voltage, it should be handled with great care.<br />
<br />
=== FPGA board ===<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA] and features many different interfaces.<br />
The clock oscillates at 66&nbsp;MHz.<br />
<br />
=== Buttons and LEDs I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd buttons and LEDs board] is used in conjunction with the FPGA board.<br />
<br />
It has 4&nbsp;buttons and 8&nbsp;LEDs.<br />
It can hold an optional LCD display.<br />
<br />
=== Logic-level LC lowpass board ===<br />
The logic-level LC lowpass board is used to verify the content of the PWM signals in the two H-bridge branches.<br />
It smooths the two FPGA output PWM signals into the components of a differential sine wave.<br />
<br />
On this board too, the default LC cutoff frequency is something like 20&nbsp;kHz.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Inverter/laboratoires|Travaux de laboratoire]]<br />
** [[Inverter/labore|Laborprojekt]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Inverter/board combination|Board combinations]]<br />
* Additional informations for [[Inverter/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/File:Inverter_110_V_generator_setup.JPGFile:Inverter 110 V generator setup.JPG2021-11-26T07:04:59Z<p>Francois.corthay: uploaded a new version of &quot;File:Inverter 110 V generator setup.JPG&quot;</p>
<hr />
<div></div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE_labs/presentations/PWMEln/ETE labs/presentations/PWM2021-11-19T13:39:59Z<p>Francois.corthay: /* Unipolar load */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
<br />
The PWM modulator is used to drive power loads from a digital circuit.<br />
<br />
= Unipolar load =<br />
<br />
Show a motor, a power supply and a switch:<br />
[[File:ElN labs PWM1.svg|75px|center]]<br />
<br />
Explain the PWM control with the sawtooth signal.<br />
[[File:ElN labs PWM3.svg|200px|center]]<br />
<br />
Modify the circuit to have 2 switches building a half bridge.<br />
This forces not only the power supply but also the ground on the load.<br />
[[File:ElN labs PWM2.svg|200px|center]]<br />
<br />
= Bipolar load =<br />
<br />
If one wants to have voltages and currents in both directions, one needs a full H-bridge.<br />
[[File:ElN labs PWM4.svg|300px|center]]<br />
<br />
Explain the functionality with the idea to switch one side fix and PWM on the other.<br />
<br />
-> draw mean voltages on 2 branches and differential voltage on the load.</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE/teacherEln/ETE/teacher2021-11-15T14:39:31Z<p>Francois.corthay: /* To Do */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
<br />
= Lab presentations =<br />
<br />
A little information allows to drive the students into the labs:<br />
* [[Eln/ETE labs/presentations/PHA|Lab PHA]]<br />
* [[Eln/ETE labs/presentations/NUM|Lab NUM]]<br />
* [[Eln/ETE labs/presentations/ADD|Lab ADD]]<br />
* [[Eln/ETE labs/presentations/MUL|Lab MUL]]<br />
* [[Eln/ETE labs/presentations/COR|Lab COR]]<br />
* [[Eln/ETE labs/presentations/PHD|Lab PHD]]<br />
* [[Eln/ETE labs/presentations/PWM|Lab PWM]]<br />
* [[Eln/ETE labs/presentations/COM|Lab ART]]<br />
<br />
= To Do =<br />
<br />
COR :<br />
* Update lab specidication (take away pipeline)<br />
* prepare an architecture with a loop to increase the precision<br />
<br />
PWM<br />
- vérifier la disparition des xxx_masterVersion dans les versions étudiants</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE/teacherEln/ETE/teacher2021-11-10T17:51:09Z<p>Francois.corthay: /* To Do */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
<br />
= Lab presentations =<br />
<br />
A little information allows to drive the students into the labs:<br />
* [[Eln/ETE labs/presentations/PHA|Lab PHA]]<br />
* [[Eln/ETE labs/presentations/NUM|Lab NUM]]<br />
* [[Eln/ETE labs/presentations/ADD|Lab ADD]]<br />
* [[Eln/ETE labs/presentations/MUL|Lab MUL]]<br />
* [[Eln/ETE labs/presentations/COR|Lab COR]]<br />
* [[Eln/ETE labs/presentations/PHD|Lab PHD]]<br />
* [[Eln/ETE labs/presentations/PWM|Lab PWM]]<br />
* [[Eln/ETE labs/presentations/COM|Lab ART]]<br />
<br />
= To Do =<br />
<br />
COR :<br />
* Update lab specidication (take away pipeline)<br />
* prepare an architecture with a loop to increase the precision</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE/teacherEln/ETE/teacher2021-11-08T15:38:06Z<p>Francois.corthay: /* Lab presentations */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
<br />
= Lab presentations =<br />
<br />
A little information allows to drive the students into the labs:<br />
* [[Eln/ETE labs/presentations/PHA|Lab PHA]]<br />
* [[Eln/ETE labs/presentations/NUM|Lab NUM]]<br />
* [[Eln/ETE labs/presentations/ADD|Lab ADD]]<br />
* [[Eln/ETE labs/presentations/MUL|Lab MUL]]<br />
* [[Eln/ETE labs/presentations/COR|Lab COR]]<br />
* [[Eln/ETE labs/presentations/PHD|Lab PHD]]<br />
* [[Eln/ETE labs/presentations/PWM|Lab PWM]]<br />
* [[Eln/ETE labs/presentations/COM|Lab ART]]<br />
<br />
= To Do =<br />
<br />
COR :<br />
* Update lab specidication (take away pipeline)<br />
* prepare an architecture with a loop to increase the precision<br />
* add/sub tester : have X different from Y and same with x- y-shifted (e.g. invert bits)</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Inverter/board_combinationInverter/board combination2021-11-08T10:46:35Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! [http://wiki.hevs.ch/uit/index.php5?title=Hardware/Parallelport/heb_inverter Inverter board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Ribbon cable<br/>long/short || Power cable<br/>12V/5V<br />
! Group<br />Members || Comment<br />
|-<br />
| ETE-1 || 22 || 11 || 01 || 11 || yes || 1/1 || 1/1 || || with serial port<br />
|-<br />
| ETE-2 || 02 || 12 || 02 || 12 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-3 || 03 || 13 || 03 || 13 || yes || 1/1 || 1/1 || || <br />
|-<br />
| ETE-4 || 04 || 14 || 04 || 14 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-5 || 05 || 05 || 05 || 15 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-6 || 06 || 16 || 06 || 16 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-7 || 07 || 17 || 07 || 17 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-8 || 15 || 18 || 08 || 18 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-9 || 16 || 09 || 09 || 19 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-10 || 17 || 06 || 10 || 10 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-11 || 70 || 08 || 11 || 06 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-12 || 12 || 02 || 12 || 02 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-13 || 13 || 03 || 13 || 03 || yes || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-14 || 14 || 04 || 14 || 04 || yes || 1/1 || 1/1 || ||<br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Inverter/board_combinationInverter/board combination2021-11-08T09:41:31Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! [http://wiki.hevs.ch/uit/index.php5?title=Hardware/Parallelport/heb_inverter Inverter board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Ribbon cable<br/>long/short || Power cable<br/>12V/5V<br />
! Group<br />Members || Comment<br />
|-<br />
| ETE-1 || 22 || 11 || 01 || 11 || no || 1/1 || 1/1 || || with serial port<br />
|-<br />
| ETE-2 || 02 || 12 || 02 || 12 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-3 || 03 || 13 || 03 || 13 || no || 1/1 || 1/1 || || <br />
|-<br />
| ETE-4 || 04 || 14 || 04 || 14 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-5 || 05 || 05 || 05 || 15 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-6 || 06 || 16 || 06 || 16 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-7 || 07 || 17 || 07 || 17 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-8 || 08 || 18 || 08 || 18 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-9 || 16 || 09 || 09 || 19 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-10 || 17 || 06 || 10 || 10 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-11 || 70 || 08 || 11 || 06 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-12 || 12 || 02 || 12 || 02 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-13 || 13 || 03 || 13 || 03 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-14 || 14 || 04 || 14 || 04 || no || 1/1 || 1/1 || ||<br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/File:COR2.svgFile:COR2.svg2021-10-29T13:49:22Z<p>Francois.corthay: uploaded a new version of &quot;File:COR2.svg&quot;</p>
<hr />
<div></div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/File:Cor1.svgFile:Cor1.svg2021-10-29T10:31:46Z<p>Francois.corthay: uploaded a new version of &quot;File:Cor1.svg&quot;</p>
<hr />
<div>Cordic rotation in a single direction</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/labsEln/labs2021-10-15T08:12:05Z<p>Francois.corthay: /* Schedule */</p>
<hr />
<div>{{TOC right}}<br />
<br />
= Labs environment =<br />
<br />
The labs environment is found on [https://github.com/hei-ete-8132-eln/eln_labs/ GitHub].<br />
Students can use [https://git-scm.com/ Git] for version control if they want,<br />
but they can also only download the [https://github.com/hei-synd-2131-eln/eln_labs/archive/master.zip ZIP].<br />
<br />
The laboratory specifications are found on [https://cyberlearn.hes-so.ch CyberLearn].<br />
<br />
{{TaskBox|content=<br />
Download the labs environment to <br />
<code>U:\ElN_labs</code> or any other folder.<br />
{{WarningBox|content=<br />
Make sure that there are no spaces nor other special characters in the destination path.}}<br />
}}<br />
<br />
= Schedule =<br />
<br />
The labs sequence is&nbsp;:<br />
{| class="wikitable" style="margin: 20pt"<br />
! index || short || title<br />
|-<br />
| style="text-align:center" | 1 || [[Eln/Labs/PHA|PHA]] || Phase accuracy display<br/>(introduction to the tools)<br />
|-<br />
| style="text-align:center" | 2 || NUM || Binary and arithmetic numbers<br />
|-<br />
| style="text-align:center" | 3 || ADD || Binary adder<br />
|-<br />
| style="text-align:center" | 4 || MUL || Multiplier<br />
|-<br />
| style="text-align:center" | 5 || rowspan=3 | in odd years COR<br/>in even years PHD || rowspan=3 | Sinus generator<br/>Phase detector<br />
|-<br />
| style="text-align:center" | 6<br />
|-<br />
| style="text-align:center" | 7 <br />
|-<br />
| style="text-align:center" | 8 || PWM || Pulse-width modulation<br />
|-<br />
| style="text-align:center" | 9 || ART || Serial communication link<br />
|-<br />
| style="text-align:center" |10 - 15|| in odd years Inverter<br/>in even years Synchro || project<br />
|}<br />
<br />
= Additional Information =<br />
<br />
* Additional informations [[Eln/ETE/teacher|for teachers]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Inverter/board_combinationInverter/board combination2021-10-14T10:10:04Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! [http://wiki.hevs.ch/uit/index.php5?title=Hardware/Parallelport/heb_inverter Inverter board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Ribbon cable<br/>long/short || Power cable<br/>12V/5V<br />
! Group<br />Members || Comment<br />
|-<br />
| ETE-1 || 22 || 11 || 01 || 11 || no || 1/1 || 1/1 || || with serial port<br />
|-<br />
| ETE-2 || 02 || 12 || 02 || 12 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-3 || 03 || 13 || 03 || 13 || no || 1/1 || 1/1 || || <br />
|-<br />
| ETE-4 || 04 || 14 || 04 || 14 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-5 || 05 || 05 || 05 || 15 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-6 || 06 || 16 || 06 || 16 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-7 || 07 || 17 || 07 || 17 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-8 || 08 || 18 || 08 || 18 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-9 || 16 || 02 || 09 || 19 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-10 || 17 || 04 || 10 || 10 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-11 || 70 || 06 || 11 || 06 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-12 || 12 || 08 || 12 || 02 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-13 || 13 || 09 || 13 || 03 || no || 1/1 || 1/1 || ||<br />
|-<br />
| ETE-14 || 14 || xx || 14 || 04 || no || 1/1 || 1/1 || ||<br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Inverter/board_combinationInverter/board combination2021-10-08T15:36:47Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! inverter board<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Power<br/>cable || Ribbon cable<br/>long/short<br />
! Group<br />Members || Comment<br />
|-<br />
| ETE-1 || 22 || 11 || 01 || 11 || no || || || || with serial port<br />
|-<br />
| ETE-2 || 02 || 12 || 02 || 12 || no || || || ||<br />
|-<br />
| ETE-3 || 03 || 13 || 03 || 13 || no || || || || <br />
|-<br />
| ETE-4 || 04 || 14 || 04 || 14 || no || || || ||<br />
|-<br />
| ETE-5 || 05 || 05 || 05 || 15 || no || || || ||<br />
|-<br />
| ETE-6 || 06 || 16 || 06 || 16 || no || || || ||<br />
|-<br />
| ETE-7 || 07 || 17 || 07 || 17 || no || || || ||<br />
|-<br />
| ETE-8 || 08 || 18 || 08 || 18 || no || || || ||<br />
|-<br />
| ETE-9 || 16 || 02 || 09 || 19 || no || || || ||<br />
|-<br />
| ETE-10 || 17 || 04 || 10 || 10 || no || || || ||<br />
|-<br />
| ETE-11 || 70 || 06 || 11 || 06 || no || || || ||<br />
|-<br />
| ETE-12 || 12 || 08 || 12 || 02 || no || || || ||<br />
|-<br />
| ETE-13 || 13 || 09 || 13 || 03 || no || || || ||<br />
|-<br />
| ETE-14 || 14 || xx || 14 || 04 || no || || || ||<br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Inverter/board_combinationInverter/board combination2021-10-08T15:14:38Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! inverter board<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Power<br/>cable || Ribbon cable<br/>long/short<br />
! Group<br />Members || Comment<br />
|-<br />
| ETE-1 || 22 || 11 || 01 || 01 || no || || || || with serial port<br />
|-<br />
| ETE-2 || 02 || 12 || 02 || 02 || no || || || ||<br />
|-<br />
| ETE-3 || 03 || 13 || 03 || 03 || no || || || || <br />
|-<br />
| ETE-4 || 04 || 14 || 04 || 04 || no || || || ||<br />
|-<br />
| ETE-5 || 05 || 15 || 05 || 05 || no || || || ||<br />
|-<br />
| ETE-6 || 06 || 16 || 06 || 06 || no || || || ||<br />
|-<br />
| ETE-7 || 07 || 17 || 07 || 07 || no || || || ||<br />
|-<br />
| ETE-8 || 08 || 18 || 08 || 08 || no || || || ||<br />
|-<br />
| ETE-9 || 16 || 19 || 09 || 09 || no || || || ||<br />
|-<br />
| ETE-10 || 17 || 20 || 10 || 10 || no || || || ||<br />
|-<br />
| ETE-11 || 70 || 21 || 11 || 11 || no || || || ||<br />
|-<br />
| ETE-12 || 12 || 22 || 12 || 12 || no || || || ||<br />
|-<br />
| ETE-13 || 13 || 23 || 13 || 13 || no || || || ||<br />
|-<br />
| ETE-14 || 14 || 24 || 14 || 14 || no || || || ||<br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Synchro/board_combinationSynchro/board combination2021-10-08T15:02:36Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! Synchro board<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Power<br/>cable || Ribbon cable<br/>long/short<br />
! Group<br />Members || Comment<br />
|- <br />
| ETE-1 || 22 || 11 || 91 || 1 || no || x || 1/1 || || with serial port<br />
|- <br />
| ETE-2 || 02 || 12 || 92 || 2 || no || x || 1/1 || ||<br />
|- <br />
| ETE-3 || 03 || 13 || 93 || 3 || no || x || 1/1 || || scan chain not seen<br />
|- <br />
| ETE-4 || 04 || 14 || 94 || 4 || no || x || 1/1 || ||<br />
|- <br />
| ETE-5 || 05 || 15 || 95 || 5 || no || x || 1/1 || || <br />
|- <br />
| ETE-6 || 06 || 16 || 96 || 6 || no || x || 1/1 || ||<br />
|- <br />
| ETE-7 || 07 || 17 || 97 || 7 || no || x || 1/1 || ||<br />
|- <br />
| ETE-8 || 08 || 18 || 98 || 8 || no || x || 1/1 || ||<br />
|- <br />
| ETE-9 || 16 || 19 || 99 || 9 || no || x || 0/1 || ||<br />
|- <br />
| ETE-10 || 17 || 20 || 95 || 10 || no || x || 0/1 || ||<br />
|- <br />
| ETE-11 || 70 || 21 || 96 || 11 || no || x || 1/1 || ||<br />
|- <br />
| ETE-12 || 12 || 22 || 97 || 12 || no || x || 1/1 || ||<br />
|- <br />
| ETE-13 || 13 || 23 || 98 || 13 || no || x || 1/1 || ||<br />
|- <br />
| ETE-14 || 14 || 24 || 99 || 14 || no || x || 1/1 || ||<br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Synchro]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Inverter/board_combinationInverter/board combination2021-10-08T15:01:48Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! inverter board<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Group<br />Members || Comment<br />
|-<br />
| ETE-1 || 22 || 11 || 01 || 01 || no || || with serial port<br />
|-<br />
| ETE-2 || 02 || 12 || 02 || 02 || no || ||<br />
|-<br />
| ETE-3 || 03 || 13 || 03 || 03 || no || || <br />
|-<br />
| ETE-4 || 04 || 14 || 04 || 04 || no || ||<br />
|-<br />
| ETE-5 || 05 || 15 || 05 || 05 || no || ||<br />
|-<br />
| ETE-6 || 06 || 16 || 06 || 06 || no || ||<br />
|-<br />
| ETE-7 || 07 || 17 || 07 || 07 || no || ||<br />
|-<br />
| ETE-8 || 08 || 18 || 08 || 08 || no || ||<br />
|-<br />
| ETE-9 || 16 || 19 || 09 || 09 || no || ||<br />
|-<br />
| ETE-10 || 17 || 20 || 10 || 10 || no || ||<br />
|-<br />
| ETE-11 || 70 || 21 || 11 || 11 || no || ||<br />
|-<br />
| ETE-12 || 12 || 22 || 12 || 12 || no || ||<br />
|-<br />
| ETE-13 || 13 || 23 || 13 || 13 || no || ||<br />
|-<br />
| ETE-14 || 14 || 24 || 14 || 14 || no || ||<br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Inverter/board_combinationInverter/board combination2021-10-08T14:59:29Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! inverter board<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Group<br />Members || Comment<br />
|-<br />
| ETE-1 || 22 || 11 || 01 || || no || || with serial port<br />
|-<br />
| ETE-2 || 02 || 12 || 02 || || no || ||<br />
|-<br />
| ETE-3 || 03 || 13 || 13 || || no || || <br />
|-<br />
| ETE-4 || 04 || 14 || 04 || || no || ||<br />
|-<br />
| ETE-5 || 05 || 15 || 05 || || no || ||<br />
|-<br />
| ETE-6 || 06 || 16 || 06 || || no || ||<br />
|-<br />
| ETE-7 || 07 || 17 || 07 || || no || ||<br />
|-<br />
| ETE-8 || 08 || 18 || 08 || || no || ||<br />
|-<br />
| ETE-9 || 16 || 19 || 09 || || no || ||<br />
|-<br />
| ETE-10 || 17 || 20 || 10 || || no || ||<br />
|-<br />
| ETE-11 || 70 || 21 || 11 || || no || ||<br />
|-<br />
| ETE-12 || 12 || 22 || 12 || || no || ||<br />
|-<br />
| ETE-13 || 13 || 23 || 12 || || no || ||<br />
|-<br />
| ETE-14 || 14 || 24 || 12 || || no || ||<br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Inverter/board_combinationInverter/board combination2021-10-08T14:56:09Z<p>Francois.corthay: </p>
<hr />
<div>{{TOC right}}<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#v2 Lowpass<br />filter]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Mez#PWM Mezzanine<br />C-board ]<br />
! H-Bridge || power<br />lowpass || EEPROM<br />Programmed || Group<br />Members || Comment<br />
|-<br />
| ETE-1 || 22 || 11 || 01 || 91 || 71 || 21 || 51 || no || ||<br />
|-<br />
| ETE-2 || 02 || 12 || 02 || 92 || 72 || 22 || 52 || no || ||<br />
|-<br />
| ETE-3 || 03 || 13 || 13 || 93 || 73 || 23 || 53 || no || || <br />
|-<br />
| ETE-4 || 04 || 14 || 04 || 94 || 74 || 24 || 54 || no || ||<br />
|-<br />
| ETE-5 || 05 || 15 || 05 || 95 || 75 || 25 || 55 || no || ||<br />
|-<br />
| ETE-6 || 06 || 16 || 06 || 96 || 76 || 26 || 56 || no || ||<br />
|-<br />
| ETE-7 || 07 || 17 || 07 || 97 || 77 || 27 || 57 || no || ||<br />
|-<br />
| ETE-8 || 08 || 18 || 08 || 98 || 78 || 28 || 58 || no || ||<br />
|-<br />
| ETE-9 || 16 || 19 || 09 || 99 || 79 || 29 || 59 || no || ||<br />
|-<br />
| ETE-10 || 17 || 20 || 10 || 100 || 70 || 20 || 50 || no || ||<br />
|-<br />
| ETE-11 || 70 || 21 || 11 || 101 || 81 || || || no || ||<br />
|-<br />
| ETE-12 || 12 || 22 || 12 || 102 || 82 || || || no || ||<br />
|-<br />
| ETE-13 || 13 || 23 || 12 || 102 || 82 || || || no || ||<br />
|-<br />
| ETE-14 || 14 || 24 || 12 || 102 || 82 || || || no || ||<br />
|}<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Inverter]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Synchro/board_combinationSynchro/board combination2021-10-08T14:49:19Z<p>Francois.corthay: /* Lab boxes */</p>
<hr />
<div>{{TOC right}}<br />
<br />
= Lab boxes =<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! Synchro board<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Power<br/>cable || Ribbon cable<br/>long/short<br />
! Group<br />Members || Comment<br />
|- <br />
| ETE-1 || 22 || 11 || 91 || 1 || no || x || 1/1 || || with serial port<br />
|- <br />
| ETE-2 || 02 || 12 || 92 || 2 || no || x || 1/1 || ||<br />
|- <br />
| ETE-3 || 03 || 13 || 93 || 3 || no || x || 1/1 || || scan chain not seen<br />
|- <br />
| ETE-4 || 04 || 14 || 94 || 4 || no || x || 1/1 || ||<br />
|- <br />
| ETE-5 || 05 || 15 || 95 || 5 || no || x || 1/1 || || <br />
|- <br />
| ETE-6 || 06 || 16 || 96 || 6 || no || x || 1/1 || ||<br />
|- <br />
| ETE-7 || 07 || 17 || 97 || 7 || no || x || 1/1 || ||<br />
|- <br />
| ETE-8 || 08 || 18 || 98 || 8 || no || x || 1/1 || ||<br />
|- <br />
| ETE-9 || 16 || 19 || 99 || 9 || no || x || 0/1 || ||<br />
|- <br />
| ETE-10 || 17 || 20 || 95 || 10 || no || x || 0/1 || ||<br />
|- <br />
| ETE-11 || 70 || 21 || 96 || 11 || no || x || 1/1 || ||<br />
|- <br />
| ETE-12 || 12 || 22 || 97 || 12 || no || x || 1/1 || ||<br />
|- <br />
| ETE-13 || 13 || 23 || 98 || 13 || no || x || 1/1 || ||<br />
|- <br />
| ETE-14 || 14 || 24 || 99 || 14 || no || x || 1/1 || ||<br />
|}<br />
<br />
= Inventory =<br />
<br />
* [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGAboards]<br />
* [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer programmers]<br />
* [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_Synchro synchro boards]<br />
* [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 buttons boards]<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Synchro]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Synchro/board_combinationSynchro/board combination2021-10-08T14:38:45Z<p>Francois.corthay: /* Lab boxes */</p>
<hr />
<div>{{TOC right}}<br />
<br />
= Lab boxes =<br />
<br />
{|class=wikitable style="text-align:center"<br />
! ID<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGA Board]<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer Programmer]<br />
! Synchro board<br />
! [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 Buttons and<br />LEDs board]<br />
! EEPROM<br />Programmed || Power<br/>cable || Ribbon cable<br/>long/short<br />
! Group<br />Members || Comment<br />
|- <br />
| ETE-1 || 22 || 21 || 91 || 1 || no || x || 1/1 || || with serial port<br />
|- <br />
| ETE-2 || 02 || 22 || 92 || 2 || no || x || 1/1 || ||<br />
|- <br />
| ETE-3 || 03 || 23 || 93 || 3 || no || x || 1/1 || || scan chain not seen<br />
|- <br />
| ETE-4 || 04 || 24 || 94 || 4 || no || x || 1/1 || ||<br />
|- <br />
| ETE-5 || 05 || 25 || 95 || 5 || no || x || 1/1 || || <br />
|- <br />
| ETE-6 || 06 || 26 || 96 || 6 || no || x || 1/1 || ||<br />
|- <br />
| ETE-7 || 07 || 27 || 97 || 7 || no || x || 1/1 || ||<br />
|- <br />
| ETE-8 || 08 || 28 || 98 || 8 || no || x || 1/1 || ||<br />
|- <br />
| ETE-9 || 16 || 29 || 99 || 9 || no || x || 0/1 || || X<br />
|- <br />
| ETE-10 || 17 || 30 || 95 || 10 || no || x || 0/1 || || X<br />
|- <br />
| ETE-11 || 70 || 31 || 96 || 11 || no || x || 1/1 || ||<br />
|- <br />
| ETE-12 || 12 || 32 || 97 || 12 || no || x || 1/1 || ||<br />
|- <br />
| ETE-13 || 13 || 33 || 98 || 13 || no || x || 1/1 || ||<br />
|- <br />
| ETE-14 || 14 || 34 || 99 || 14 || no || x || 1/1 || || X<br />
|}<br />
<br />
X : requires soldering the 3 buttons<br />
<br />
= Inventory =<br />
<br />
* [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_FPGA-EBS#Student FPGAboards]<br />
* [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_Programmer#Digilent_Xilinx_Programmer programmers]<br />
* [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_Synchro synchro boards]<br />
* [http://wiki.hevs.ch/uit/index.php5/Hardware/Stock_PP#HEB_LCD_V1.0_.28a.k.a._Buttons_.26_LEDs.29 buttons boards]<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Synchro]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/ETE/teacherEln/ETE/teacher2020-11-27T13:10:35Z<p>Francois.corthay: /* Lab presentations */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
<br />
= Lab presentations =<br />
<br />
A little information allows to drive the students into the labs:<br />
* [[Eln/ETE labs/presentations/PHA|Lab PHA]]<br />
* [[Eln/ETE labs/presentations/NUM|Lab NUM]]<br />
* [[Eln/ETE labs/presentations/ADD|Lab ADD]]<br />
* [[Eln/ETE labs/presentations/MUL|Lab MUL]]<br />
* [[Eln/ETE labs/presentations/COR|Lab COR]]<br />
* [[Eln/ETE labs/presentations/PHD|Lab PHD]]<br />
* [[Eln/ETE labs/presentations/PWM|Lab PWM]]<br />
* [[Eln/ETE labs/presentations/COM|Lab ART]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/Eln/labsEln/labs2020-11-27T13:10:09Z<p>Francois.corthay: /* Schedule */</p>
<hr />
<div>{{TOC right}}<br />
<br />
= Labs environment =<br />
<br />
The labs environment is found on [https://github.com/hei-ete-8132-eln/eln_labs/ GitHub].<br />
Students can use [https://git-scm.com/ Git] for version control if they want,<br />
but they can also only download the [https://github.com/hei-synd-2131-eln/eln_labs/archive/master.zip ZIP].<br />
<br />
The laboratory specifications are found on [https://cyberlearn.hes-so.ch CyberLearn].<br />
<br />
{{TaskBox|content=<br />
Download the labs environment to <br />
<code>U:\ElN_labs</code> or any other folder.<br />
{{WarningBox|content=<br />
Make sure that there are no spaces nor other special characters in the destination path.}}<br />
}}<br />
<br />
= Schedule =<br />
<br />
The labs sequence is&nbsp;:<br />
{| class="wikitable" style="margin: 20pt"<br />
! index || short || title<br />
|-<br />
| style="text-align:center" | 1 || [[Eln/Labs/PHA|PHA]] || Phase accuracy display<br/>(introduction to the tools)<br />
|-<br />
| style="text-align:center" | 2 || NUM || Binary and arithmetic numbers<br />
|-<br />
| style="text-align:center" | 3 || ADD || Binary adder<br />
|-<br />
| style="text-align:center" | 4 || MUL || Multiplier<br />
|-<br />
| style="text-align:center" | 5 || rowspan=3 | in odd years COR<br/>in even years PHD || rowspan=3 | Sinus generator<br/>Phase detector<br />
|-<br />
| style="text-align:center" | 6<br />
|-<br />
| style="text-align:center" | 7 <br />
|-<br />
| style="text-align:center" | 8 || PWM || Pulse-width modulation<br />
|-<br />
| style="text-align:center" | 9 || ART || Serial communication link<br />
|-<br />
| style="text-align:center" |10 - 15|| || project<br />
|}<br />
<br />
= Additional Information =<br />
<br />
* Additional informations [[Eln/ETE/teacher|for teachers]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/SynchroSynchro2020-11-20T08:15:14Z<p>Francois.corthay: /* Components */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The [http://energie-techniques-environnementales.hevs.ch/ Filière Energie et Techniques environnementales] (FET)<br />
has the digital systems course and labs in the 3rd (autumn) semester.<br />
The semester counts 15 weeks and ends with a little project.<br />
The aim of the [https://en.wikipedia.org/wiki/Synchronization_(alternating_current) generator synchronzation] project is to align an AC motor used as a generator to a reference 50&nbsp;HZ signal.<br />
<br />
[[File:Synchro Motors.jpg|400px|center|thumb|Motor and Generator]]<br />
<br />
== Specification ==<br />
<br />
=== Function ===<br />
<br />
The reference signal and the generator output are digitized to 1&nbsp;bit with the help of two comparators.<br />
The digital circuit receives these signals and controls a DC&nbsp;motor coupled to the generator.<br />
<br />
[[File:Synchro system.svg|500px|center|thumb|Synchro Schematic]]<br />
<br />
The circuit can be controlled by 4&nbsp;buttons.<br />
It can display information on a row of 8&nbsp;LEDs.<br />
<br />
=== Circuit ===<br />
<br />
The circuit works as follows:<br />
* the difference between the mains period and the generator period is calculated<br />
* if the generator is too slow, the DC motor voltage is raised; if the generator is too fast, the DC motor voltage is diminished<br />
<br />
== Components ==<br />
<br />
The system consists of<br />
* an [[Synchro#Motor-generator assembly|assembly of a DC motor and an AC generator]]<br />
* an [[Synchro#FPGA_board|FPGA prototyping board]]<br />
<!--<br />
* an [[Synchro#Synchro_I.2FO_board|I/O board]] with 2 sinewave inputs and a PWM output<br />
--><br />
* an [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd user board] with 4 buttons and 8 LEDs<br />
<br />
=== Motor-generator assembly ===<br />
The DC motor is controlled via a 12&nbsp;V PWM signal.<br />
It is mechanically coupled to the DC generator.<br />
With a mean voltage of 6&nbsp;V, the assembly turns at a frequency close to 50&nbsp;Hz.<br />
<br />
=== FPGA board ===<br />
The main board is the school's [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGAEBS FPGA-EBS lab development board].<br />
It hosts a [http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html Xilinx Spartan xc3s500e FPGA]<br />
and features many different interfaces.<br />
Its quartz oscillator provides a clock of 66&nbsp;MHz.<br />
<br />
=== Synchro I/O board ===<br />
<br />
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_synchro HEB-synchro] I/O board receives 2&nbsp;sinewaves: one from a 50&nbsp;Hz function generator and one from the AC generator.<br />
These signals are converted to 3.3&nbsp;V logic levels by<br />
[http://www.nxp.com/products/discretes-and-logic/logic/hct/hex-inverting-schmitt-trigger:74HC14D CMOS Schmitt triggers] for the FPGA.<br />
The 50&nbsp;Hz analog input should have the proper amplitude and offset to fit within the 0&nbsp;V to 3.3&nbsp;V power supply range.<br />
<br />
The FPGA delivers a PWM output which controls a power switch.<br />
The switch then drives the DC motor.<br />
The PWM frequency should be smaller than 100&nbsp;kHz.<br />
<br />
== Getting started ==<br />
In order to start the projects you should do the following:<br />
* Read carefully the specifications above<br />
* Draw the architecture of the circuit in the form of a block diagram<br />
* Consult the guides for the first steps into the design software<br />
** [[Synchro/students_fr|Guide en français]]<br />
** [[Synchro/students_de|Anleitung auf Deutsch]]<br />
<br />
== Additional Information ==<br />
<br />
* [[Synchro/board combination|Board combinations]]<br />
* Additional informations for [[Synchro/teachers|teachers]].<br />
<br />
[[Category:Bachelor]] [[Category:ElN]] [[Category:Synchro]]</div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/File:ElN_labs_PHD3.svgFile:ElN labs PHD3.svg2020-11-02T14:32:15Z<p>Francois.corthay: uploaded a new version of &quot;File:ElN labs PHD3.svg&quot;: changed input to blue
offseted the time line</p>
<hr />
<div></div>Francois.corthayhttps://wiki.hevs.ch/ete/index.php5/File:ElN_labs_PHD3.svgFile:ElN labs PHD3.svg2020-11-02T11:54:48Z<p>Francois.corthay: uploaded a new version of &quot;File:ElN labs PHD3.svg&quot;: removed a dangling arrow</p>
<hr />
<div></div>Francois.corthay