Synchro
From ETE
Revision as of 15:49, 1 December 2014 by Francois.corthay (Talk | contribs)
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The Filière Energie et Techniques environnementales (FET) has the digital systems course and labs in the 3rd (autumn) semester. The semester counts 15 weeks and ends with a little project.
The aim to the project is to synchronise an AC motor used as a generator to a reference 50 HZ signal.
Specification
Function
The reference signal and the generator output are digitised to 1 bit with the help of two comparators. The digital circuit receives these signals and controls a DC motor coupled to the generator.
Circuit
Components
The system consists of
- an assembly of a DC motor and an AC generator
- an FPGA prototyping board
- a synchro I/O board with 2 sinewave inputs and a PWM output
Motor generator assembly
FPGA board
The main board is the school's FPGA-EBS lab development board. It hosts a Xilinx Spartan xc3s500e FPGA and features many different interfaces.
Synchro I/O board
Semester organization
Week schedule
| Week | Course | Lab |
|---|---|---|
| 1 | NUM / COM | PHA - phase accuracy display (introduction to the tools) |
| 2 | COM / KAR | NUM - numbers and operations |
| 3 | KAR / MUX | ADD - binary adder |
| 4 | MUX / LST | MUL - multiplier |
| 5 | LST / LAT | PHD - phase detector |
| 6 | LAT | PHD |
| 7 | CNT | PHU - phase unwrapper |
| 8 | FSM | COM - Serial port receiver |
| 9 - 15 | project |
