https://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&feed=atom&action=historyKart/FPGA board - Revision history2024-03-29T14:49:29ZRevision history for this page on the wikiMediaWiki 1.18.1https://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=2849&oldid=prevFrancois.corthay: /* Test */2021-09-03T08:33:19Z<p><span class="autocomment">Test</span></p>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The system is powered via a circular connector which connects to a 3.3&nbsp;V regulator.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The system is powered via a circular connector which connects to a 3.3&nbsp;V regulator.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>5&nbsp;V is a good power voltage candidate.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>5&nbsp;V is a good power voltage candidate.</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">== Sniffer ==</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">The RS232 to USB [[Media:Kart USB-RS232 board.pdf|board]] can be used as an FPGA mezzanine</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">with only the FTDI USB to RS232 chip mounted.</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[Category:Kart]]</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[Category:Kart]]</div></td></tr>
</table>Francois.corthayhttps://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=2830&oldid=prevFrancois.corthay: /* Test */2021-08-19T11:19:03Z<p><span class="autocomment">Test</span></p>
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<td colspan='2' style="background-color: white; color:black;">Revision as of 11:19, 19 August 2021</td>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>== Test ==</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>== Test ==</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div>A test board routes the FPGA motherboard connector pins from one to the next.</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>A <ins class="diffchange diffchange-inline">[[Media:Kart tester board.pdf|</ins>test board<ins class="diffchange diffchange-inline">]] </ins>routes the FPGA motherboard connector pins</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>from one to the next.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The path also includes the SCL and SDA pins of the bus connector.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The path also includes the SCL and SDA pins of the bus connector.</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div>The path <del class="diffchange diffchange-inline">extermities </del>are located on spare I/Os of the JTAG programming connector.</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>The path <ins class="diffchange diffchange-inline">extremities </ins>are located on spare I/Os of the JTAG programming connector.</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div>Each pair of pins are also connected to a <del class="diffchange diffchange-inline">diode</del>, which shows to what extent the signal path is functional.</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>Each pair of pins are also connected to a <ins class="diffchange diffchange-inline">LED</ins>, which shows to what extent the signal path is functional.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Kart fpga test board.JPG|center|400px|FPGA motherboard]]</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Kart fpga test board.JPG|center|400px|FPGA motherboard]]</div></td></tr>
</table>Francois.corthayhttps://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=2722&oldid=prevFrancois.corthay at 14:42, 1 July 20202020-07-01T14:42:09Z<p></p>
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<td colspan='2' style="background-color: white; color:black;">Revision as of 14:42, 1 July 2020</td>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>{{TOC right}}</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>{{TOC right}}</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div>The FPGA motherboards are equipped with an AGL125 [http://www.microsemi.com/products/fpga-soc/fpga/igloo-overview IGLOO] in a VQ100 package and a 10 MHz Quartz.</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>The <ins class="diffchange diffchange-inline">[[Media:Kart Control V40.pdf|</ins>FPGA motherboards<ins class="diffchange diffchange-inline">]] </ins>are equipped with</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>an AGL125 [http://www.microsemi.com/products/fpga-soc/fpga/igloo-overview IGLOO] in a VQ100 package and a 10 MHz Quartz.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Fpga board.jpg|center|200px|FPGA motherboard]]</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Fpga board.jpg|center|200px|FPGA motherboard]]</div></td></tr>
</table>Francois.corthayhttps://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=2122&oldid=prevFrancois.corthay: /* Connection */2017-08-22T13:31:36Z<p><span class="autocomment">Connection</span></p>
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<td colspan='2' style="background-color: white; color:black;">Revision as of 13:31, 22 August 2017</td>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The daughterboards connect on the two single row connectors on the long sides.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The daughterboards connect on the two single row connectors on the long sides.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The mounting screws on 3&nbsp;corners only are used to secure against placing the daughter board the wrong way round.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The mounting screws on 3&nbsp;corners only are used to secure against placing the daughter board the wrong way round.</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">The following figure shows the pinning in case of test needs:</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">[[File:Kart FPGA boards pins.svg|center|FPGA board pingnni]]</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>== Test ==</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>== Test ==</div></td></tr>
</table>Francois.corthayhttps://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=1909&oldid=prevOliver.gubler at 14:14, 24 August 20162016-08-24T14:14:11Z<p></p>
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<td colspan='2' style="background-color: white; color:black;">Revision as of 14:14, 24 August 2016</td>
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<td colspan="2" class="diff-lineno">Line 1:</td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>{{TOC right}}</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>{{TOC right}}</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div>The FPGA motherboards are equipped with an AGL125 [http://www.microsemi.com/products/fpga-soc/fpga/igloo-overview IGLOO] in a VQ100 package.</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>The FPGA motherboards are equipped with an AGL125 [http://www.microsemi.com/products/fpga-soc/fpga/igloo-overview IGLOO] in a VQ100 package <ins class="diffchange diffchange-inline">and a 10 MHz Quartz</ins>.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Fpga board.jpg|center|200px|FPGA motherboard]]</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Fpga board.jpg|center|200px|FPGA motherboard]]</div></td></tr>
</table>Oliver.gublerhttps://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=1449&oldid=prevFrancois.corthay at 08:20, 2 July 20152015-07-02T08:20:43Z<p></p>
<table class='diff diff-contentalign-left'>
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<td colspan='2' style="background-color: white; color:black;">Revision as of 08:20, 2 July 2015</td>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The path extermities are located on spare I/Os of the JTAG programming connector.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The path extermities are located on spare I/Os of the JTAG programming connector.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>Each pair of pins are also connected to a diode, which shows to what extent the signal path is functional.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>Each pair of pins are also connected to a diode, which shows to what extent the signal path is functional.</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">[[File:Kart fpga test board.JPG|center|400px|FPGA motherboard]]</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>A square wave is sent from one extermity to the other, thus having half of the pins working as outputs and the other half working as inputs.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>A square wave is sent from one extermity to the other, thus having half of the pins working as outputs and the other half working as inputs.</div></td></tr>
</table>Francois.corthayhttps://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=1447&oldid=prevFrancois.corthay: /* Test */2015-07-02T08:06:46Z<p><span class="autocomment">Test</span></p>
<table class='diff diff-contentalign-left'>
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<td colspan='2' style="background-color: white; color:black;">Revision as of 08:06, 2 July 2015</td>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>A test board routes the FPGA motherboard connector pins from one to the next.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>A test board routes the FPGA motherboard connector pins from one to the next.</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">The path also includes the SCL and SDA pins of the bus connector.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">The path extermities are located on spare I/Os of the JTAG programming connector.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">Each pair of pins are also connected to a diode, which shows to what extent the signal path is functional.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">A square wave is sent from one extermity to the other, thus having half of the pins working as outputs and the other half working as inputs.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">A switch allows to invert the path's direction, thus changing the I/O mode of all the pins.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">The system is powered via a circular connector which connects to a 3.3&nbsp;V regulator.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">5&nbsp;V is a good power voltage candidate.</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[Category:Kart]]</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[Category:Kart]]</div></td></tr>
</table>Francois.corthayhttps://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=1445&oldid=prevFrancois.corthay: /* Connection */2015-07-02T07:57:14Z<p><span class="autocomment">Connection</span></p>
<table class='diff diff-contentalign-left'>
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<td colspan='2' style="background-color: white; color:black;">← Older revision</td>
<td colspan='2' style="background-color: white; color:black;">Revision as of 07:57, 2 July 2015</td>
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<td colspan="2" class="diff-lineno">Line 12:</td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The daughterboards connect on the two single row connectors on the long sides.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The daughterboards connect on the two single row connectors on the long sides.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The mounting screws on 3&nbsp;corners only are used to secure against placing the daughter board the wrong way round.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The mounting screws on 3&nbsp;corners only are used to secure against placing the daughter board the wrong way round.</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">== Test ==</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">A test board routes the FPGA motherboard connector pins from one to the next.</ins></div></td></tr>
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</table>Francois.corthayhttps://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=1379&oldid=prevFrancois.corthay at 12:11, 2 June 20152015-06-02T12:11:19Z<p></p>
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<td colspan='2' style="background-color: white; color:black;">Revision as of 12:11, 2 June 2015</td>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The FPGA motherboards are equipped with an AGL125 [http://www.microsemi.com/products/fpga-soc/fpga/igloo-overview IGLOO] in a VQ100 package.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>The FPGA motherboards are equipped with an AGL125 [http://www.microsemi.com/products/fpga-soc/fpga/igloo-overview IGLOO] in a VQ100 package.</div></td></tr>
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<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div>[[File:Fpga board.jpg|center|200px|<del class="diffchange diffchange-inline">Demo Kart</del>]]</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>[[File:Fpga board.jpg|center|200px|<ins class="diffchange diffchange-inline">FPGA motherboard</ins>]]</div></td></tr>
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<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins class="diffchange diffchange-inline">== Connection ==</ins></div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>They have two I2C connectors on one side and the programming connector on the other side.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>They have two I2C connectors on one side and the programming connector on the other side.</div></td></tr>
</table>Francois.corthayhttps://wiki.hevs.ch/fsi/index.php5?title=Kart/FPGA_board&diff=1376&oldid=prevFrancois.corthay: Created page with "{{TOC right}} The FPGA motherboards are equipped with an AGL125 [http://www.microsemi.com/products/fpga-soc/fpga/igloo-overview IGLOO] in a VQ100 package. [[File:Fpga board...."2015-06-02T12:05:29Z<p>Created page with "{{TOC right}} The FPGA motherboards are equipped with an AGL125 [http://www.microsemi.com/products/fpga-soc/fpga/igloo-overview IGLOO] in a VQ100 package. [[File:Fpga board...."</p>
<p><b>New page</b></p><div>{{TOC right}}<br />
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The FPGA motherboards are equipped with an AGL125 [http://www.microsemi.com/products/fpga-soc/fpga/igloo-overview IGLOO] in a VQ100 package.<br />
<br />
[[File:Fpga board.jpg|center|200px|Demo Kart]]<br />
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They have two I2C connectors on one side and the programming connector on the other side.<br />
The I2C connectors allow daisy chaining either with fixed-length PCBs or with flat cables.<br />
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The daughterboards connect on the two single row connectors on the long sides.<br />
The mounting screws on 3&nbsp;corners only are used to secure against placing the daughter board the wrong way round.<br />
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[[Category:Kart]]</div>Francois.corthay