Libero IDE presentation
Libero IDE is used to program the Microchip FPGAs.
The main design files are located in
The Physical Design Constraints
.pdc file specifies the I/O locations and electric levels.
Further design files are found in
$DESIGN.prjx synthesis/$DESIGN_syn.prj designer/impl1/$DESIGN.adb designer/impl1/$DESIGN.ide_des designer/impl1/$DESIGN.pdb
This second set of files is copied into a temporary directory which will be additionally populated by the numerous design files generated by the deign tool.
Launching the tools is done in two steps.
- with the top-level block selected, the
prepare for synthesistask does the following:
- the design tool generates a single VHDL file
trimLibs.plscript replaces all library definitions with the one of
Libero Project Navigatortask does the following:
Update prjx.plscript updates the paths specified in the
.prjxfile to reflect the project location's.
- the Libero IDE is launched
Interactive run of the Libero tools
To check the synthesis and downnload results wit a better accuracy, one can start Libero IDE and go through:
- Synthesize -> open interactively
- implementation option -> specify clock frequency
- view log
- Compile -> open interactively
- I/O Attibute Editor
- Programming File
- FlashPro -> open interactively
- verify programmer