https://wiki.hevs.ch/uit/api.php5?action=feedcontributions&user=Admin+uit&feedformat=atomUIT - User contributions [en]2024-03-29T05:48:11ZUser contributionsMediaWiki 1.18.1https://wiki.hevs.ch/uit/index.php5/Template:Private_deepskinTemplate:Private deepskin2017-01-24T14:21:36Z<p>Admin uit: </p>
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</noinclude></div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Main_PageMain Page2016-06-24T10:54:32Z<p>Admin uit: /* News */</p>
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= Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit =<br />
{{TOC right}}<br />
[[File:hesso_logo.png|left|200px|HESSO Valais Wallis Logo|link=http://www.hevs.ch]]<br />
This is the knowledge database of the [http://www.hevs.ch HES-SO Valais Wallis]<br />
[http://www.hevs.ch/en/rad-instituts/institute-of-systems-engineering/ Institute of Systems Engineering] Infotronics Unit (UIT).<br />
It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.<br />
<br />
Find more information about our educational program in the [http://wiki.hevs.ch/fsi FSI Wiki].<br />
<br />
[[File:Icontexto-inside-rss.png|link=Help:http://wiki.hevs.ch/uit/index.php?title=Special:RecentChanges&feed=rss|48px]] [http://wiki.hevs.ch/uit/index.php?title=Special:RecentChanges&feed=rss Get informed about all changes to this wiki by signing up to this RSS feed]<br />
<br />
= Getting started =<br />
Use the ''Navigation'' to the left to enter the different sections or follow any of the following links:<br />
* [[Help:Contents|Help]]<br />
* [//meta.wikimedia.org/wiki/Help:Contents Wikimedia's Help]<br />
* [//www.mediawiki.org/wiki/Manual:FAQ MediaWiki FAQ]<br />
* [[Sandbox|Sandbox for test purposes]]<br />
<br />
= News =<br />
<br />
{{NewsBox|First [[GroupFPGA]] meeting|2016-02-24|<br />
The [[GroupFPGA]] has been founded to bring together all the collaborators at HEI instersted in programmable logic. <br />
The first meeting was accompanied by a presentation of the [https://spinalhdl.github.io/SpinalDoc/ SpinalHDL] by its inventor [https://fr.linkedin.com/in/charles-papon-9645476b Charles Papon]. A workshop about this language is planned in the near future.<br />
}}<br />
{{NewsBox|''[https://www.raspberrypi.org/products/raspberry-pi-3-model-b/ Raspberry Pi 3]'' has been released|2016-02-29|<br />
The ''[https://www.raspberrypi.org/products/raspberry-pi-3-model-b/ Raspberry Pi 3]'' finally has built-in 802.11n Wi-Fi and Bluetooth 4.0 (and BLE) and still only costs 35$. In comparison to the ''Raspberry Pi 2'', the processor is about 50% faster with the 64-bit, 1.2 GHz ARM Cortex A53 and the graphics chips' speed is increased to 400 MHz. On the other side, the maximal current consumption is increased to 2.5 A.<br />
}}<br />
{{NewsBox|The freshest version of [http://www.qt.io/ide/ QtCreator] now includes an [http://doc.qt.io/qtcreator/creator-modeling.html UML-Editor]|2015-12-15|<br />
The [http://doc.qt.io/qtcreator/creator-modeling.html Modeling-Editor] is still an early version, therefore it has to be activated in ''Help -> Plugin -> ModelEditor'' but it supports already Package, Class, Component, Use case and Activity diagrams. Elements can be added to the graphical view not only from the toolbar or the elements tree, but also by dropping source files on it.<br />
}}<br />
{{NewsBox|''HyperCam'' hyperspectral camera|2015-10-16|<br />
Microsoft Research and the Universitiy of Washington just released a paper describing a camera that takes pictures at 17 different wavelengths.<br />
* [https://goo.gl/DNMyNV Video]<br />
* [http://www.geekwire.com/2015/see-through-snapshots-microsoft-and-uw-tech-takes-pictures-that-are-more-than-skin-deep Article at GeekWire]<br />
}}<br />
{{NewsBox|''SpinalHDL'' introduction in complex HDL projects|2015-07-21|<br />
''SpinalHDL'', a very new high level hardware description library, is now used on the HDL complex design ''xADDACore'' - a fully auto-generated and customizable architecture for wide-band impedance spectroscopy (compatible with multiple hardware, some targeted projects : ''HiSADDA'', ''IGOR V'', ''MiniBioDet'' and ''OLGM''). <br />
More details on :<br />
* [http://spinalhdl.github.io/SpinalHDL/ ''SpinalHDL'' Website]<br />
* [https://github.com/SpinalHDL ''SpinalHDL'' Git]<br />
* [https://github.com/SpinalHDL/SpinalDoc/blob/master/presentation/en/presentation.pdf ''SpinalHDL'' Presentation slides]<br />
}}<br />
{{NewsBox|''[[Tools/Mentor_HDL_Designer|HDL-Designer]] [[Tools/Versions#2015.1|2015.1]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|2015-04-21|<br />
* VHDL 2008 enhancements<br />
* SystemVerilog Assistant<br />
* Xilinx Vivado interface<br />
* bugfixes and minor enhancements}}<br />
{{NewsBox|''[[Tools/Mentor_Modelsim|Model-]]/[[Tools/Mentor_Questasim|QuestaSim]] 10.4a'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|2015-04-07|<br />
* Performance improvements for SV (OVM/UVM), VHDL, HTML and libraries<br />
* New Toolbars (Edit Preferences)<br />
* discontinued support for Windows XP and Vista!}}<br />
{{NewsBox|''[[Tools/Synopsys_Synplify|Synplify]] [[Tools/Versions#2015.03|2015.3]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|2015-03-12|<br />
* Compiler Enhancements<br />
* ...}}<br />
{{NewsBox|''[https://sourceforge.net/p/winpython WinPython] 2.7.9.3 is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|2015-03-02|<br />
* new packages: numpy, jsonschema, mistune, ...<br />
* upgraded many packages<br />
[[Category:Python]]}}<br />
{{NewsBox|[http://www.qt.io/download-open-source/# ''Qt 5.4''] including [http://www.qt.io/download-open-source/#section-6 ''Qt Creator 3.3.0''] has been released|2013-12-12|<br />
Check the [http://goo.gl/aTrF0i Summary of New Features]<br />
}}<br />
{{NewsBox|''[[Tools/Microsemi_Libero|Microsemi Libero SoC]] [[Tools/Versions#11.4|11.4]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|2014-08-07|<br />
* Enlarged support for ''SmartFusion2'' and ''IGLOO2'' families<br />
* Runtime and UI improvements<br />
* ''SoftConsole v3.4 requires the SP1 to be compatible with Libero SoC v11.4''}}<br />
{{NewsBox|''[[Tools/Xilinx_ISE|Xilinx ISE]] [[Tools/Versions#14.7|14.7]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|2014-03-18|<br />
IMPORTANT: As ISE enters it's ''sustaining phase of product life'' there will be '''no more major releases'''. However, updates and patches might still be released.<br />
* 7 series and Zynq device and IP updates}}<br />
{{NewsBox|New Heavyweight FPGA Champion: [http://www.xilinx.com/ Xilinx] [http://press.xilinx.com/2013-12-10-Xilinx-Doubles-Industrys-Highest-Capacity-Device-to-4-4M-Logic-Cells-Delivering-Density-Advantage-that-is-a-Full-Generation-Ahead announced] the new ''Virtex UltraScale All Programmable devices''|2013-12-11|<br />
This 3D IC contains three die (SLR) to achieve:<br />
* 4.4M logic cells (approx. 50M ASIC gates)<br />
* 88.6 Mbits BRAM<br />
* 2880 DSP48 slices (4268 GMACs/sec)<br />
* hard-IPs: 6 x PCIe, 3 x 100G Ethernet MAC, 48 x 16.3 Gbps transceivers<br />
* 1456 I/O Pins<br />
}}<br />
{{NewsBox|In need of a Qt Library? Like to publish one? Check out [http://inqlude.org/ #in''q''lude]!|2013-11-29|<br />
Inqlude is meant to be the place where you find all information and pointers to Qt libraries, components or modules. There's the webpage, a format for describing Q-based libraries and a command line client to install libraries. It's all still in alpha phase, but certainly worth a look. For more and up-to-date information follow this [http://bit.ly/1b82cY7 link].}}<br />
{{NewsBox|''[[Tools/Xilinx_ISE|Xilinx ISE]] [[Tools/Versions#14.6|14.6]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|2013-07-18|<br />
* IP updates<br />
* further Device Support for Zynq-7000 and Defenense-Grade Zynq-7000Q, Artix-7Q, Virtex-7Q}}<br />
{{NewsBox|IGLOO for the masses: [http://www.microsemi.com/ Microsemi] [http://bit.ly/1bUCQy5 announced] the new ''[http://www.microsemi.com/fpga-soc/fpga/igloo2-fpga IGLOO2 FPGA]''|2013-06-19|<br />
Like the old IGLOOs, it's based on the non-volatile Flash technology, with it's advantages of independence from external configuration devices, lower power (flash freeze), higher radiation immunity and security. Up until now, Flash based devices have been rather small. But with IGLOO2, Microsemi is now in direct competition with the other important FPGA manufacturers. IGLOO2 has<br />
* 6-150 kLUTs (like Xilinx Artix-7 or Spartan6)<br />
* up to 16 5G SerDes (competitors: <10)<br />
* max. 574 User IOs (like Spartan6, more than Artix-7)<br />
* 700-5000 kBits RAM<br />
* up to 2 DDR controllers and 4 PCIe endpoints<br />
The M2GL050 is already shipping and starts at less than $7USD for high volume orders.<br />
}}<br />
{{NewsBox|''[http://osvvm.org/ OSVVM] release 2013.05 is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|2013-05-31|<br />
* adds large vector randomization<br />
* has a work around for some Aldec issues}}<br />
{{NewsBox|The ''IEEE Std 1800-2012'' a.k.a. ''SystemVerilog'' is available for [http://standards.ieee.org/getieee/1800/download/1800-2012.pdf download]||<br />
The '''31 new features''', '''60 clarifications''' and '''71 corrections''' of the standard include:<br />
* Multiple inheritance !<br />
* ''Soft'' constraints<br />
* Uniqueness constraints<br />
* A different global clock can be defined for each hierarchy scope<br />
More infos [http://www.sutherland-hdl.com/papers/2012-DVCon_SystemVerilog-2012_presentation.pdf here]}}<br />
{{NewsBox|UIT Wiki Presentation||<br />
The presentation slides can be downloaded [[Media:Presentation_en_UITWiki.pdf|here]].}}<br />
{{NewsBox|''UVM 1.1b''||This bugfix release is available for download now.}}</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/GroupFPGAGroupFPGA2016-06-24T10:48:12Z<p>Admin uit: </p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
= Definition =<br />
The GroupFPGA has been formed with the goal to unite the collaborators at HEI interested in programmable logic.<br />
<br />
Informal meetings will be held once every one to two months.<br />
<br />
= Members =<br />
In alphabetic order by last name.<br />
<br />
* [[User:Christop.bianchi|Christophe Bianchi]]<br />
* [[User:Francois.corthay|François Corthay]]<br />
* [[User:Alexandr.ganchinh|Alexandre Ganchinho]]<br />
* [[User:Oliver.gubler|Oliver Gubler]]<br />
* [[User:Christop.metraill|Christopher Metrailler]]<br />
* [[User:Pierrean.mudry|Pierre-Andre Mudry]]<br />
* [[User:Marc.pignat|Marc Pignat]]<br />
* [http://www.hevs.ch/fr/rad-instituts/institut-systemes-industriels/collaborateurs/professeure-hes/pompili-1649 Pierre Pompili]<br />
* [[User:Charles.praplan|Charles Praplan]]<br />
* [[User:Alexandr.sierro|Alexandre Sierro]]</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/GroupFPGAGroupFPGA2016-06-24T10:47:21Z<p>Admin uit: Created page with "{{private}} {{TOC right}} The GroupFPGA has been formed with the goal to unite the collaborators at HEI interested in programmable logic. Informal meetings will be held once ..."</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
The GroupFPGA has been formed with the goal to unite the collaborators at HEI interested in programmable logic.<br />
<br />
Informal meetings will be held once every one to two months.<br />
<br />
Members (in alphabetic order by last name):<br />
<br />
* [[User:Christop.bianchi|Christophe Bianchi]]<br />
* [[User:Francois.corthay|François Corthay]]<br />
* [[User:Alexandr.ganchinh|Alexandre Ganchinho]]<br />
* [[User:Oliver.gubler|Oliver Gubler]]<br />
* [[User:Christop.metraill|Christopher Metrailler]]<br />
* [[User:Pierrean.mudry|Pierre-Andre Mudry]]<br />
* [[User:Marc.pignat|Marc Pignat]]<br />
* [http://www.hevs.ch/fr/rad-instituts/institut-systemes-industriels/collaborateurs/professeure-hes/pompili-1649 Pierre Pompili]<br />
* [[User:Charles.praplan|Charles Praplan]]<br />
* [[User:Alexandr.sierro|Alexandre Sierro]]</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/MediaWiki:SidebarMediaWiki:Sidebar2016-06-24T10:01:07Z<p>Admin uit: </p>
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* Navigation<br />
** mainpage|Mainpage<br />
** tools|Tools<br />
** hardware|Hardware<br />
** inventory| ➜ Inventory<br />
** languages|Languages<br />
** components|Components<br />
** standards|Standards<br />
** projects|Projects <br />
** groupFPGA|GroupFPGA<br />
** links|Links <br />
** articles|Articles<br />
** helppage|help<br />
<br />
<br />
* Browse<br />
** Special:Categories|Categories<br />
** Special:AllPages|All Pages<br />
** recentchanges-url|recentchanges<br />
<!-- This is a comment** randompage-url|randompage --><br />
<br />
* SEARCH<br />
* TOOLBOX<br />
* LANGUAGES</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Moule_cmd.xlsFile:Moule cmd.xls2016-03-08T08:15:59Z<p>Admin uit: uploaded a new version of &quot;File:Moule cmd.xls&quot;</p>
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<div></div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Tools/VersionsTools/Versions2016-03-08T07:23:07Z<p>Admin uit: /* Mentor Questa */</p>
<hr />
<div>{{TOC right}}<br />
<br />
This is a list of the tools and the corresponding version we use in our projects. <br />
You can find the files in two places:<br />
* T:\Applications\<br />
* [ftp://fpga:fpga@153.109.5.248 Oliver's Software Server]<br />
<br />
For space improvements, only versions related to a project in the list below are kept on [ftp://fpga:fpga@153.109.5.248 Oliver's Software Server].<br />
<br />
{{NewsBox|@Students||<br />
* For laboratory work use the '''''Labo''''' version.<br />
* For semester or diploma work, follow the recommendations of your professor/assistant.}}<br />
<br />
== [[Tools/Mentor_HDL_Designer|Mentor HDL-Designer]] ==<br />
<br />
=== version 2015.1 vs. 2009.2 ===<br />
+- vector range has to be entered completely manually, no more dropdown for <downto>,<to><br />
<br />
=== 2015.1 ===<br />
* Dormouse<br />
<br />
=== 2012.1 ===<br />
* [[Projects#USLO|USLO]]<br />
<br />
=== 2011.1 ===<br />
* [[Projects#PTP|PTP]]<br />
* VIPC<br />
<br />
=== 2009.2 ===<br />
* '''''Labo / EDA libs'''''<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
* ADELE<br />
* BasMI<br />
* VerifThin<br />
* [[Projects#EzCat|EzCat]]<br />
* PureDigital<br />
* OLGM<br />
<br />
=== 2007 ===<br />
* HRTM<br />
<br />
== Mentor Modelsim ==<br />
Of the different revisions (a,b,c,...) only the latest will be kept.<br />
<br />
=== 10.5 ===<br />
<br />
=== 10.4 ===<br />
* Dormouse<br />
==== version 10.4 vs. 6.6 ====<br />
+ constants are visible in Objects List and can be added to Waveform<br />
<br />
+ show vector and array indexes<br />
<br />
+ capitalization same as in VHDL<br />
<br />
+ base can be shown<br />
<br />
+ Global Signal Radix<br />
<br />
+ marks In-/Outputs<br />
<br />
+ shows which signals are not logged in Objects View<br />
<br />
- does not mark FSMs<br />
<br />
- BUG: setting base does not work if multiple signals selected<br />
=== 10.3 ===<br />
* [[Projects#USLO|USLO]]<br />
<br />
=== 10.2 ===<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
<br />
=== 6.6 ===<br />
* '''''Labo / EDA libs'''''<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
* ADELE<br />
* BasMI<br />
* VerifThin<br />
* [[Projects#EzCat|EzCat]]<br />
* PureDigital<br />
<br />
== Mentor Questa ==<br />
Of the different revisions (a,b,c,...) only the latest will be kept.<br />
<br />
=== 10.5 ===<br />
<br />
=== 10.1 ===<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
* [[Projects#PTP|PTP]]<br />
<br />
=== 10.0 ===<br />
* HW-XF<br />
* VIPC<br />
<br />
== [[Tools/Synopsys_Synplify|Synopsys Synplify]] ==<br />
Of the different service packs (SP1,SP2,...) only the latest will be kept, as it contains all the changes from the previous SPs.<br />
<br />
=== 2015.03 ===<br />
<br />
=== 2014.09 ===<br />
* [[Projects#USLO|USLO]]<br />
<br />
=== 2014.03 ===<br />
* [[Projects#PTP|PTP]]<br />
<br />
=== 2013.09 ===<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
<br />
=== 2011.09 ===<br />
* PureDigital<br />
<br />
=== 2011.03 ===<br />
* VIPC<br />
<br />
=== 2009.06 ===<br />
* '''''Labo'''''<br />
<br />
== [[Tools/Xilinx_Vivado|Xilinx Vivado]] ==<br />
Recommended by Xilinx for 7 Series and newer. For older FPGAs use [[Tools/Xilinx_ISE|Xilinx ISE]].<br />
<br />
=== 2014.4 ===<br />
* Dormouse<br />
<br />
== [[Tools/Xilinx_ISE|Xilinx ISE]] ==<br />
Recommended by Xilinx for 6 Series and older. For newer FPGAs use [[Tools/Xilinx_Vivado|Xilinx Vivado]].<br />
<br />
=== 14.7 - last major release===<br />
* Dormouse<br />
<br />
=== 14.5 ===<br />
* '''''Labo 13'''''<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
* [[Projects#USLO|USLO]]<br />
* [[Projects#PTP|PTP]]<br />
<br />
=== 13.4 ===<br />
* BroadEnc<br />
<br />
=== 12.1 ===<br />
* '''''Labo / EDA libs'''''<br />
* [[Projects#EzCat|EzCat]]<br />
* PureDigital<br />
<br />
=== 9.2 ===<br />
* VerifThin<br />
<br />
== [[Tools/Microsemi_Libero|Microsemi Libero]] ==<br />
Of the different service packs (SP1,SP2,...) only the latest will be kept, as it contains all the changes from the previous SPs.<br />
<br />
Recommended by Microsemi:<br />
* Libero SoC [[Tools/Versions#11.0|v11.0]] for ''SmartFusion2'', ''SmartFusion'', ''Fusion'', ''ProASIC3'', ''IGLOO'', ''IGLOO2'' and ''Fusion'' families<br />
* Libero IDE [[Tools/Versions#9.1|v9.1]] for older families<br />
<br />
=== 11.5 ===<br />
<br />
=== 11.0 ===<br />
* '''''Labo 13'''''<br />
<br />
=== 10.0 ===<br />
* HW-XF<br />
<br />
=== 9.1 ===<br />
* '''''Labo'''''<br />
* PureDigital</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Tools/VersionsTools/Versions2016-03-08T07:22:57Z<p>Admin uit: /* Mentor Modelsim */</p>
<hr />
<div>{{TOC right}}<br />
<br />
This is a list of the tools and the corresponding version we use in our projects. <br />
You can find the files in two places:<br />
* T:\Applications\<br />
* [ftp://fpga:fpga@153.109.5.248 Oliver's Software Server]<br />
<br />
For space improvements, only versions related to a project in the list below are kept on [ftp://fpga:fpga@153.109.5.248 Oliver's Software Server].<br />
<br />
{{NewsBox|@Students||<br />
* For laboratory work use the '''''Labo''''' version.<br />
* For semester or diploma work, follow the recommendations of your professor/assistant.}}<br />
<br />
== [[Tools/Mentor_HDL_Designer|Mentor HDL-Designer]] ==<br />
<br />
=== version 2015.1 vs. 2009.2 ===<br />
+- vector range has to be entered completely manually, no more dropdown for <downto>,<to><br />
<br />
=== 2015.1 ===<br />
* Dormouse<br />
<br />
=== 2012.1 ===<br />
* [[Projects#USLO|USLO]]<br />
<br />
=== 2011.1 ===<br />
* [[Projects#PTP|PTP]]<br />
* VIPC<br />
<br />
=== 2009.2 ===<br />
* '''''Labo / EDA libs'''''<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
* ADELE<br />
* BasMI<br />
* VerifThin<br />
* [[Projects#EzCat|EzCat]]<br />
* PureDigital<br />
* OLGM<br />
<br />
=== 2007 ===<br />
* HRTM<br />
<br />
== Mentor Modelsim ==<br />
Of the different revisions (a,b,c,...) only the latest will be kept.<br />
<br />
=== 10.5 ===<br />
<br />
=== 10.4 ===<br />
* Dormouse<br />
==== version 10.4 vs. 6.6 ====<br />
+ constants are visible in Objects List and can be added to Waveform<br />
<br />
+ show vector and array indexes<br />
<br />
+ capitalization same as in VHDL<br />
<br />
+ base can be shown<br />
<br />
+ Global Signal Radix<br />
<br />
+ marks In-/Outputs<br />
<br />
+ shows which signals are not logged in Objects View<br />
<br />
- does not mark FSMs<br />
<br />
- BUG: setting base does not work if multiple signals selected<br />
=== 10.3 ===<br />
* [[Projects#USLO|USLO]]<br />
<br />
=== 10.2 ===<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
<br />
=== 6.6 ===<br />
* '''''Labo / EDA libs'''''<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
* ADELE<br />
* BasMI<br />
* VerifThin<br />
* [[Projects#EzCat|EzCat]]<br />
* PureDigital<br />
<br />
== Mentor Questa ==<br />
Of the different revisions (a,b,c,...) only the latest will be kept.<br />
<br />
=== 10.4 ===<br />
<br />
=== 10.1 ===<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
* [[Projects#PTP|PTP]]<br />
<br />
=== 10.0 ===<br />
* HW-XF<br />
* VIPC<br />
<br />
== [[Tools/Synopsys_Synplify|Synopsys Synplify]] ==<br />
Of the different service packs (SP1,SP2,...) only the latest will be kept, as it contains all the changes from the previous SPs.<br />
<br />
=== 2015.03 ===<br />
<br />
=== 2014.09 ===<br />
* [[Projects#USLO|USLO]]<br />
<br />
=== 2014.03 ===<br />
* [[Projects#PTP|PTP]]<br />
<br />
=== 2013.09 ===<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
<br />
=== 2011.09 ===<br />
* PureDigital<br />
<br />
=== 2011.03 ===<br />
* VIPC<br />
<br />
=== 2009.06 ===<br />
* '''''Labo'''''<br />
<br />
== [[Tools/Xilinx_Vivado|Xilinx Vivado]] ==<br />
Recommended by Xilinx for 7 Series and newer. For older FPGAs use [[Tools/Xilinx_ISE|Xilinx ISE]].<br />
<br />
=== 2014.4 ===<br />
* Dormouse<br />
<br />
== [[Tools/Xilinx_ISE|Xilinx ISE]] ==<br />
Recommended by Xilinx for 6 Series and older. For newer FPGAs use [[Tools/Xilinx_Vivado|Xilinx Vivado]].<br />
<br />
=== 14.7 - last major release===<br />
* Dormouse<br />
<br />
=== 14.5 ===<br />
* '''''Labo 13'''''<br />
* [[Projects#PoUSSyERE|PoUSSyERE]]<br />
* [[Projects#USLO|USLO]]<br />
* [[Projects#PTP|PTP]]<br />
<br />
=== 13.4 ===<br />
* BroadEnc<br />
<br />
=== 12.1 ===<br />
* '''''Labo / EDA libs'''''<br />
* [[Projects#EzCat|EzCat]]<br />
* PureDigital<br />
<br />
=== 9.2 ===<br />
* VerifThin<br />
<br />
== [[Tools/Microsemi_Libero|Microsemi Libero]] ==<br />
Of the different service packs (SP1,SP2,...) only the latest will be kept, as it contains all the changes from the previous SPs.<br />
<br />
Recommended by Microsemi:<br />
* Libero SoC [[Tools/Versions#11.0|v11.0]] for ''SmartFusion2'', ''SmartFusion'', ''Fusion'', ''ProASIC3'', ''IGLOO'', ''IGLOO2'' and ''Fusion'' families<br />
* Libero IDE [[Tools/Versions#9.1|v9.1]] for older families<br />
<br />
=== 11.5 ===<br />
<br />
=== 11.0 ===<br />
* '''''Labo 13'''''<br />
<br />
=== 10.0 ===<br />
* HW-XF<br />
<br />
=== 9.1 ===<br />
* '''''Labo'''''<br />
* PureDigital</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Tools/Xilinx_VivadoTools/Xilinx Vivado2016-03-01T07:49:20Z<p>Admin uit: /* Vivado stalls when opening a target */</p>
<hr />
<div>{{TOC right}}<br />
<br />
= Rescue measures =<br />
<br />
== 2014.4 ==<br />
<br />
=== Vivado stalls when opening a target ===<br />
* this happens when you unplug the programmer or powercycle the FPGA while a target is open<br />
# kill the task ''hw_server.exe''<br />
# restart Vivado<br />
<br />
=== strange messages in the Messages view ===<br />
# right-click -> Discard old messages</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Inventory/Labo/Eln/ChronoInventory/Labo/Eln/Chrono2016-01-04T14:07:57Z<p>Admin uit: /* Eln-Chrono v2.1 */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
== [[Eln-Chrono v2.1]] ==<br />
[[File:FPGA_EBS_Motor_v2_1.jpg|thumb|Eln-Chrono V2.1 (a.k.a. FPGA-EBS Motor v2.1)]]<br />
{|class=wikitable<br />
|-<br />
! Board Number || Stock Location || Usage Location / User / Project || Remarks<br />
|-<br />
| 10 || A201 || || <br />
|- <br />
| 11 || A201 || || <br />
|-<br />
| 12 || A201 || || <br />
|-<br />
| 13 || A201 || || <br />
|-<br />
| 14 || A201 || || <br />
|-<br />
| 15 || A201 || || <br />
|-<br />
| 16 || A201 || || <br />
|-<br />
| 17 || A201 || || <br />
|-<br />
| 18 || A201 || || burnt<br />
|-<br />
| 19 || A201 || || motor seems to have the coils wrongly connected<br />
|-<br />
| 20 || A201 || || in production<br />
|- <br />
| 21 || A201 || || in production<br />
|-<br />
| 22 || A201 || || in production<br />
|-<br />
| 23 || A201 || || in production<br />
|-<br />
| 24 || A201 || || in production<br />
|-<br />
| 25 || A201 || || in production<br />
|-<br />
| 26 || A201 || || in production<br />
|-<br />
| 27 || A201 || || in production<br />
|-<br />
| 28 || A201 || || in production<br />
|-<br />
| 29 || A201 || || in production<br />
|-<br />
|}<br />
<br />
== [[Eln-Chrono v1.2]] ==<br />
[[File:FPGA_PP_heb_motor_v1.jpg|thumb|Eln-Chrono V1.2]]<br />
{|class=wikitable<br />
|-<br />
! Board Number || Stock Location || Usage Location / User / Project || Remarks<br />
|-<br />
| 1 || A201 || || <br />
|- <br />
| 2 || A201 || || <br />
|-<br />
| 3 || A201 || || <br />
|-<br />
| 4 || A201 || || <br />
|-<br />
| 5 || A201 || || <br />
|-<br />
| 6 || A201 || || <br />
|-<br />
| 7 || A201 || || <br />
|-<br />
|}</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:FPGA_EBS_Motor_v2_1.jpgFile:FPGA EBS Motor v2 1.jpg2016-01-04T14:07:11Z<p>Admin uit: FPGA EBS Motor v2.1 a.k.a. ElN-Chrono v2</p>
<hr />
<div>FPGA EBS Motor v2.1 a.k.a. ElN-Chrono v2</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Inventory/Labo/Eln/ChronoInventory/Labo/Eln/Chrono2016-01-04T13:21:05Z<p>Admin uit: /* Eln-Chrono v1.2 */</p>
<hr />
<div>{{private}}<br />
{{TOC right}}<br />
== [[Eln-Chrono v2.1]] ==<br />
[[File:|thumb|Eln-Chrono V2.1]]<br />
{|class=wikitable<br />
|-<br />
! Board Number || Stock Location || Usage Location / User / Project || Remarks<br />
|-<br />
| 10 || A201 || || <br />
|- <br />
| 11 || A201 || || <br />
|-<br />
| 12 || A201 || || <br />
|-<br />
| 13 || A201 || || <br />
|-<br />
| 14 || A201 || || <br />
|-<br />
| 15 || A201 || || <br />
|-<br />
| 16 || A201 || || <br />
|-<br />
| 17 || A201 || || <br />
|-<br />
| 18 || A201 || || burnt<br />
|-<br />
| 19 || A201 || || motor seems to have the coils wrongly connected<br />
|-<br />
| 20 || A201 || || in production<br />
|- <br />
| 21 || A201 || || in production<br />
|-<br />
| 22 || A201 || || in production<br />
|-<br />
| 23 || A201 || || in production<br />
|-<br />
| 24 || A201 || || in production<br />
|-<br />
| 25 || A201 || || in production<br />
|-<br />
| 26 || A201 || || in production<br />
|-<br />
| 27 || A201 || || in production<br />
|-<br />
| 28 || A201 || || in production<br />
|-<br />
| 29 || A201 || || in production<br />
|-<br />
|}<br />
<br />
== [[Eln-Chrono v1.2]] ==<br />
[[File:FPGA_PP_heb_motor_v1.jpg|thumb|Eln-Chrono V1.2]]<br />
{|class=wikitable<br />
|-<br />
! Board Number || Stock Location || Usage Location / User / Project || Remarks<br />
|-<br />
| 1 || A201 || || <br />
|- <br />
| 2 || A201 || || <br />
|-<br />
| 3 || A201 || || <br />
|-<br />
| 4 || A201 || || <br />
|-<br />
| 5 || A201 || || <br />
|-<br />
| 6 || A201 || || <br />
|-<br />
| 7 || A201 || || <br />
|-<br />
|}</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Help:ContentsHelp:Contents2015-10-15T15:41:09Z<p>Admin uit: /* Novell User with write rights */</p>
<hr />
<div>{{TOC right}}<br />
<br />
'''Need help for creating pages? You've come to the right place.'''<br />
<br />
== HES-SO Wiki Guidelines ==<br />
HES-SO has for this wiki some basic [[Help:Guidelines|Guidelines]] about the following themes:<br />
* [[Help:Guidelines#Page Names|Page Names]]<br />
* [[Help:Guidelines#Categories|Categories]]<br />
* [[Help:Guidelines#Navigation|Navigation]]<br />
* [[Help:Guidelines#Maintainer|Maintainer]]<br />
<br />
== Common used Syntax ==<br />
See this page for the most common used Syntax [[Help:Syntax|Shortguide for the Syntax]]<br />
* [[Help:Syntax#Access Control|Access Control]]<br />
* [[Help:Syntax#Formatting|Formatting]]<br />
* [[Help:Syntax#Tables|Tables]]<br />
* [[Help:Syntax#Links|Links]]<br />
* [[Help:Syntax#Images|Images / Files]]<br />
* [[Help:Syntax#Table of Content|Table of Content]]<br />
* [[Help:Syntax#Navigation|Navigation]]<br />
* [[Help:Syntax#Categories|Categories]]<br />
For more detailed help see also the [https://www.mediawiki.org/wiki/Help:Contents#Editing official MediaWiki Help page].<br />
<br />
== Extentions ==<br />
In this wiki you have several extentions available. See the [[Help:Extentions|Shortguide for Extentions]]<br />
* [[Help:Extentions#Math|Math]]<br />
* [[Help:Extentions#Syntax_Highlighting_Geshi|Syntax Highlighting Geshi]]<br />
* [[Help:Extentions#Subpagelist|Sub Page List]]<br />
* [[Help:Extentions#IssueTracker|Issue Tracker]]<br />
* [[Help:Extentions#Article_Comment|Article Comment]]<br />
* [[Help:Extentions#File_.26_Picture.2C_Upload_.26_Download|File & Picture Upload]]<br />
* [[Help:Extentions#RSS_Feed|RSS]]<br />
<br />
== Novell User with write rights ==<br />
There are a number of Users which have or had write privileges. See the [[Special:ListUsers|User List page]].<br />
<br />
== Special User ==<br />
* [[User:admin_uit|admin_uit]]<br />
* [[User:guest|guest]]<br />
<br />
== Useful Special Wikipages ==<br />
* [[MediaWiki:Sidebar|MediaWiki Sidebar Links]]<br />
* [[MediaWiki:Geshi.css|Geshi Extentions CSS]]<br />
* [[Default_Page|Default Template Page]]<br />
<br />
== Created Templates ==<br />
* [[special:Allpages/template:!|List of all templates]]<br />
<br />
'''Most used Templates'''<br />
* [[Template:TOC_right|TOC right template]]<br />
* [[Template:private|Private template]]<br />
* [[Template:public|Public template]]<br />
* [[Template:nav|Navigation template]]<br />
* [[Template:navNamed|Named Navigation template]]<br />
* [[Template:license|License]]<br />
<br />
<br />
[[Category:Help]]</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Template:Private_cubeclusterTemplate:Private cubecluster2015-09-15T15:15:01Z<p>Admin uit: </p>
<hr />
<div><accesscontrol>Administrators,,CubeCluster,,wikiuit(ro)</accesscontrol><br />
<table><br />
<td width="10%" valign="top">[[File:Lock_close_cubecluster.png|90px]]</td><br />
<td width="90%">{{FloatBox|center|Restricted Access|This page is only accessible to restricted users belonging to the group ''cubecluster'' or ''wikiuit''.}}</td><br />
</table><br />
<noinclude><br />
== Usage ==<br />
It allows to keep a page private and only accessible by a registered user belonging to the *cubecluster* group. Copy following code into any wiki page<br />
<pre><nowiki>{{private_cubecluster}}</nowiki> </pre><br />
</noinclude></div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Template:Private_cubeclusterTemplate:Private cubecluster2015-09-15T15:14:44Z<p>Admin uit: </p>
<hr />
<div><accesscontrol>Administrators,,CubeCluster,wikiuit(ro)</accesscontrol><br />
<table><br />
<td width="10%" valign="top">[[File:Lock_close_cubecluster.png|90px]]</td><br />
<td width="90%">{{FloatBox|center|Restricted Access|This page is only accessible to restricted users belonging to the group ''cubecluster'' or ''wikiuit''.}}</td><br />
</table><br />
<noinclude><br />
== Usage ==<br />
It allows to keep a page private and only accessible by a registered user belonging to the *cubecluster* group. Copy following code into any wiki page<br />
<pre><nowiki>{{private_cubecluster}}</nowiki> </pre><br />
</noinclude></div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Template:Private_cubeclusterTemplate:Private cubecluster2015-09-15T15:14:23Z<p>Admin uit: </p>
<hr />
<div><accesscontrol>Administrators,,CubeCluster,,wikiuit(ro)</accesscontrol><br />
<table><br />
<td width="10%" valign="top">[[File:Lock_close_cubecluster.png|90px]]</td><br />
<td width="90%">{{FloatBox|center|Restricted Access|This page is only accessible to restricted users belonging to the group ''cubecluster'' or ''wikiuit''.}}</td><br />
</table><br />
<noinclude><br />
== Usage ==<br />
It allows to keep a page private and only accessible by a registered user belonging to the *cubecluster* group. Copy following code into any wiki page<br />
<pre><nowiki>{{private_cubecluster}}</nowiki> </pre><br />
</noinclude></div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Template:Private_cubeclusterTemplate:Private cubecluster2015-09-14T14:33:50Z<p>Admin uit: </p>
<hr />
<div><accesscontrol>Administrators,,cubecluster,,wikiuit(ro)</accesscontrol><br />
<table><br />
<td width="10%" valign="top">[[File:lock_close_cubecluster.svg|90px]]</td><br />
<td width="90%">{{FloatBox|center|Restricted Access|This page is only accessible to restricted users belonging to the group ''cubecluster''.}}</td><br />
</table><br />
<noinclude><br />
== Usage ==<br />
It allows to keep a page private and only accessible by a registered user belonging to the *cubecluster* group. Copy following code into any wiki page<br />
<pre><nowiki>{{private_cubecluster}}</nowiki> </pre><br />
</noinclude></div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Introduction_paper.pdfFile:Introduction paper.pdf2014-03-20T07:34:48Z<p>Admin uit: </p>
<hr />
<div></div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-20T07:04:06Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
[[File:Seismo_logo_color.jpg|120px|float|right]]<br />
[[File:Sed_logo.jpg|200px]]<br />
[[File:Nera1.png|200px]]<br />
[[File:Euro.jpg|90px]]<br />
[[File:7 framework program logo.jpg|120px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
===Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014===<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction_paper.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
No registration fee<br><br />
No pre-registration fee<br><br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Introduction.pdfFile:Introduction.pdf2014-03-20T07:02:42Z<p>Admin uit: uploaded a new version of &quot;File:Introduction.pdf&quot;</p>
<hr />
<div>CPPS Introduction.pdf</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-20T06:55:47Z<p>Admin uit: /* Informations */</p>
<hr />
<div>__NOTOC__<br />
[[File:Seismo_logo_color.jpg|120px|float|right]]<br />
[[File:Sed_logo.jpg|200px]]<br />
[[File:Nera1.png|200px]]<br />
[[File:Euro.jpg|90px]]<br />
[[File:7 framework program logo.jpg|120px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
===Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014===<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
No registration fee<br><br />
No pre-registration fee<br><br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-20T06:55:37Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
[[File:Seismo_logo_color.jpg|120px|float|right]]<br />
[[File:Sed_logo.jpg|200px]]<br />
[[File:Nera1.png|200px]]<br />
[[File:Euro.jpg|90px]]<br />
[[File:7 framework program logo.jpg|120px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
===Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014===<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introductio]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
No registration fee<br><br />
No pre-registration fee<br><br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:ERASMUS_plus_funding_guide.pdfFile:ERASMUS plus funding guide.pdf2014-03-20T06:54:59Z<p>Admin uit: uploaded a new version of &quot;File:ERASMUS plus funding guide.pdf&quot;</p>
<hr />
<div>CPPS ERASMUS_plus_funding_guide.pdf</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Conference_location.pdfFile:Conference location.pdf2014-03-20T06:54:36Z<p>Admin uit: uploaded a new version of &quot;File:Conference location.pdf&quot;</p>
<hr />
<div>CPPS Conference_location.pdf</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Participation_costs.pdfFile:Participation costs.pdf2014-03-20T06:54:13Z<p>Admin uit: uploaded a new version of &quot;File:Participation costs.pdf&quot;</p>
<hr />
<div>CPPS Participation_costs.pdf</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Registration_Form_NERA_2014_Sion.pdfFile:Registration Form NERA 2014 Sion.pdf2014-03-20T06:53:53Z<p>Admin uit: uploaded a new version of &quot;File:Registration Form NERA 2014 Sion.pdf&quot;</p>
<hr />
<div>CPPS Registration_Form_NERA_2014_Sion.pdf</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Introduction.pdfFile:Introduction.pdf2014-03-20T06:53:32Z<p>Admin uit: uploaded a new version of &quot;File:Introduction.pdf&quot;</p>
<hr />
<div>CPPS Introduction.pdf</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:INFORMATION_guide.pdfFile:INFORMATION guide.pdf2014-03-20T06:53:13Z<p>Admin uit: uploaded a new version of &quot;File:INFORMATION guide.pdf&quot;</p>
<hr />
<div>CPPS INFORMATION_guide.pdf</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Accomodation_guide.pdfFile:Accomodation guide.pdf2014-03-20T06:52:40Z<p>Admin uit: uploaded a new version of &quot;File:Accomodation guide.pdf&quot;</p>
<hr />
<div>CPPS Accomodation_guide.pdf</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-17T12:15:40Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
[[File:Seismo_logo_color.jpg|120px|float|right]]<br />
[[File:Sed_logo.jpg|200px]]<br />
[[File:Nera1.png|200px]]<br />
[[File:Euro.jpg|90px]]<br />
[[File:7 framework program logo.jpg|120px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
===Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014===<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
No registration fee<br><br />
No pre-registration fee<br><br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-17T10:05:35Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
[[File:Seismo_logo_color.jpg|120px|float|right]]<br />
[[File:Sed_logo.jpg|200px]]<br />
[[File:Nera1.png|200px]]<br />
[[File:Euro.jpg|90px]]<br />
[[File:7 framework program logo.jpg|120px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
No registration fee<br><br />
No pre-registration fee<br><br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T14:54:07Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
[[File:Seismo_logo_color.jpg|150px|float|right]]<br />
[[File:Sed_logo.jpg|200px]]<br />
[[File:Nera1.png|200px]]<br />
[[File:Euro.jpg|100px]]<br />
[[File:7 framework program logo.jpg|120px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
No registration fee<br><br />
No pre-registration fee<br><br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T14:53:42Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
[[File:Seismo_logo_color.jpg|150px]]<br />
[[File:Sed_logo.jpg|200px]]<br />
[[File:Nera1.png|200px]]<br />
[[File:Euro.jpg|100px]]<br />
[[File:7 framework program logo.jpg|120px]]<br />
<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
No registration fee<br><br />
No pre-registration fee<br><br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T14:51:45Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
<br />
[[File:Sed_logo.jpg|200px|left]]<br />
[[File:Nera1.png|200px|left]]<br />
[[File:Euro.jpg|100px|left]]<br />
[[File:7 framework program logo.jpg|120px]]<br />
[[File:Seismo_logo_color.jpg|150px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
No registration fee<br><br />
No pre-registration fee<br><br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T14:44:36Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
<br />
[[File:Sed_logo.jpg|200px|left]]<br />
[[File:Nera1.png|200px|left]]<br />
[[File:Euro.jpg|100px|left]]<br />
[[File:7 framework program logo.jpg|120px]]<br />
[[File:Seismo_logo_color.jpg|150px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
No registration fee<br><br />
No pre-registration fee<br><br />
Payment is due 2 months before the course starts<br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T14:09:07Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
<br />
[[File:Sed_logo.jpg|200px|left]] [[File:Seismo_logo_color.jpg|150px|float|right]]<br />
[[File:Nera1.png|200px]]<br />
[[File:Euro.jpg|150px]]<br />
[[File:7 framework program logo.jpg|200px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
'''Course Fee''' : 760 CHF (accommodation non included) <br><br />
No registration fee<br><br />
No pre-registration fee<br><br />
Payment is due 2 months before the course starts<br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T14:07:30Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
<br />
[[File:Sed_logo.jpg|200px|left]] [[File:Seismo_logo_color.jpg|150px|float|right]]<br />
<br />
[[File:Nera1.png|200px]]<br />
[[File:Euro.jpg|200px]]<br />
[[File:7_framework_program_logo.png|200px]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
'''Course Fee''' : 760 CHF (accommodation non included) <br><br />
No registration fee<br><br />
No pre-registration fee<br><br />
Payment is due 2 months before the course starts<br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T14:06:40Z<p>Admin uit: </p>
<hr />
<div>__NOTOC__<br />
<br />
[[File:Sed_logo.jpg|200px|left]] [[File:Seismo_logo_color.jpg|150px|float|right]]<br />
<br />
[[File:Nera1.jpg|200px|center]]<br />
[[File:Euro.jpg|200px|center]]<br />
[[File:7_framework_program_logo.png|200px|center]]<br />
[[File:Seismology_logo.png|400px|center]]<br />
[[File:Seismology_logo.png|400px|center]]<br />
[[File:Seismology_logo.png|400px|center]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
'''Course Fee''' : 760 CHF (accommodation non included) <br><br />
No registration fee<br><br />
No pre-registration fee<br><br />
Payment is due 2 months before the course starts<br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Euro.jpgFile:Euro.jpg2014-03-14T14:05:40Z<p>Admin uit: CPPS Euro</p>
<hr />
<div>CPPS Euro</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Nera1.pngFile:Nera1.png2014-03-14T14:04:24Z<p>Admin uit: CPPS Nera</p>
<hr />
<div>CPPS Nera</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:7_framework_program_logo.jpgFile:7 framework program logo.jpg2014-03-14T14:03:57Z<p>Admin uit: CPPS 7_framework_program_logo.jpg</p>
<hr />
<div>CPPS 7_framework_program_logo.jpg</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T13:56:17Z<p>Admin uit: /* Participation Cost */</p>
<hr />
<div>__NOTOC__<br />
<br />
[[File:Sed_logo.jpg|200px|left]] [[File:Seismo_logo_color.jpg|150px|float|right]]<br />
<br />
[[File:Seismology_logo.png|400px|center]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
'''Course Fee''' : 760 CHF (accommodation non included) <br><br />
No registration fee<br><br />
No pre-registration fee<br><br />
Payment is due 2 months before the course starts<br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T09:32:53Z<p>Admin uit: /* Grants */</p>
<hr />
<div>__NOTOC__<br />
<br />
[[File:Sed_logo.jpg|200px|left]] [[File:Seismo_logo_color.jpg|150px|float|right]]<br />
<br />
[[File:Seismology_logo.png|400px|center]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
'''Course Fee''' : 760 CHF (accommodation non included) <br><br />
No pre-registration fee<br><br />
Payment is due 2 months before the course starts<br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/CPPS/WorkshopProjects/CPPS/Workshop2014-03-14T09:30:44Z<p>Admin uit: /* Grants */</p>
<hr />
<div>__NOTOC__<br />
<br />
[[File:Sed_logo.jpg|200px|left]] [[File:Seismo_logo_color.jpg|150px|float|right]]<br />
<br />
[[File:Seismology_logo.png|400px|center]]<br />
<br />
= Welcome to Seismology@School Teachers Workshop=<br />
<br />
Hes-so Valais-Wallis, Aula François- Xavier Bagnoud / Sion, 20-24 October 2014<br />
<br />
'''Organizing Institute''': SED- ETH Zürich and Hes-so Valais<br><br />
'''Chaired by''': Anne Sauron<br />
<br />
'''Scientific Committee''': Anne Sauron, Paul Denton, Stefano Solarino, Françoise Courboulex, Jean-Luc Berenguer, Aldo Zollo<br />
<br />
The workshop will run over five days in Hes-so Sion, Switzerland and will include lectures, practical sessions and field visits.<br />
<br />
== Informations ==<br />
* [[Media:Introduction.pdf|Introduction]]<br />
* [[Media:INFORMATION_guide.pdf|Information guide]]<br />
* [[Media:Accomodation_guide.pdf|Accomodation guide]]<br />
* [[Media:Conference_location.pdf|Conference Location]]<br />
<br />
== Participation Cost ==<br />
'''Course Fee''' : 760 CHF (accommodation non included) <br><br />
No pre-registration fee<br><br />
Payment is due 2 months before the course starts<br />
<br />
* [[Media:Participation_costs.pdf|Participation Costs]]<br />
<br />
== Grants ==<br />
* [[Media:ERASMUS_plus_funding_guide_1.pdf|ERASMUS plus funding guide]]<br />
* [[Media:KA1 application guidance for schools V3.pdf|KA1 application guidance for schools]]<br />
<br />
== How To Apply ==<br />
To apply for a place in the training course, please fill in the Registration Form - then a formal Invitation letter will be sent by the organizing committee. The participation will be guaranteed only after the payment will be made<br />
<br />
* [[Media:Registration_Form_NERA_2014_Sion.pdf|Registration Form Nera 2014 Sion]]<br />
<br />
== Contacts ==<br />
'''Please contact''': Anne Sauron <br><br />
'''Mail''': anne@sed.ethz.ch <br><br />
'''Tel''': +41 (0)7 89 13 15 76</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:Hesso_logo.pngFile:Hesso logo.png2014-02-28T10:28:12Z<p>Admin uit: uploaded a new version of &quot;File:Hesso logo.png&quot;</p>
<hr />
<div>HES-SO Valais Wallis Logo</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Template:Private_ptpTemplate:Private ptp2014-02-28T07:44:19Z<p>Admin uit: </p>
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<div><accesscontrol>Administrators,,ptp</accesscontrol><br />
<table><br />
<td width="10%" valign="top">[[File:lock_close.png|90px]]</td><br />
<td width="90%">{{FloatBox|center|Restricted Access|This page is only accessible to restricted users belonging to the group ''ptp''.}}</td><br />
</table><br />
<noinclude><br />
== Usage ==<br />
It allows to keep a page private and only accessible by a registered Novell user. Copy following code into any wiki page<br />
<pre><nowiki>{{private_ptp}}</nowiki> </pre><br />
</noinclude></div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Template:Private_ptpTemplate:Private ptp2014-02-28T07:44:08Z<p>Admin uit: Created page with "<accesscontrol>Administrators,,ptp</accesscontrol> <table> <td width="10%" valign="top">90px</td> <td width="90%">{{FloatBox|center|Restricted Access|T..."</p>
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<table><br />
<td width="10%" valign="top">[[File:lock_close.png|90px]]</td><br />
<td width="90%">{{FloatBox|center|Restricted Access|This page is only accessible to restricted users belonging to the group ''ptp''.}}</td><br />
</table><br />
<noinclude><br />
== Usage ==<br />
It allows to keep a page private and only accessible by a registered Novell user. Copy following code into any wiki page<br />
<pre><nowiki>{{private}}</nowiki> </pre><br />
</noinclude></div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Projects/PTPProjects/PTP2014-02-28T07:43:32Z<p>Admin uit: </p>
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<div>{{private_ptp}}<br />
{{TOC right}}<br />
<br />
PTP was an internal research project on the [[Standards/Ethernet_PTP|IEEE Std 1588 - Precision Time Protocol]]. A diploma work with the same topic has been executed by Johan Droz in 2012. While Droz concentrated on the [[Standards/Ethernet_PTP#Offset|two-step sync_msg mechanism]], the project PTP focused on the [[Standards/Ethernet_PTP#Offset|one-step sync mechanism]]. In this case the timestamping is carried out by the [[Standards/Ethernet_PTP/DP83640|NS DP83640 Precision PHYTER]].<br />
<br />
An FPGA is used to control the [[Standards/Ethernet_PTP/DP83640|phyter]]. The [[Hardware/FPGARack|HES-SO FPGA Rack Board]] holds a [[Standards/Ethernet_PTP/DP83640|DP83640]] connected to a Spartan-6 LX FPGA. During this project we used the [[Hardware/Stock_FPGA#FPGA_Rack_V1.0|XC6SLX100]] variant. Furthermore the USB port on these [[Hardware/FPGARack|boards]] is used in RS232 mode to send the collected timestamps to a computer and to access the [[Standards/Ethernet_PTP/DP83640|phyter's]] registers.<br />
A dedicated RS232 terminal has been developed to capture the timestamps on the computer and store them in a CSV file. This tool is written with C++/Qt.<br />
<br />
A PTP node can be assigned to be master or slave. As master it sends a [[Standards/Ethernet_PTP/frames#Sync_message|Sync message]] on the Ethernet interface every second. Upon reception of a [[Standards/Ethernet_PTP/frames#Delay_Req_message|Delay_Request]] a [[Standards/Ethernet_PTP/frames#Delay_Resp_message|Delay_Response]] is returned. A slave sends a [[Standards/Ethernet_PTP/frames#Delay_Req_message|Delay_Request]] every time a [[Standards/Ethernet_PTP/frames#Sync_message|Sync message]] is received. When the [[Standards/Ethernet_PTP/frames#Delay_Resp_message|Delay_Response]] arrives, all collected timestamps are sent out via RS232.<br />
<br />
All project data are accessible on the [https://repos.hevs.ch/svn/PTP/ PTP svn repository]. All path descriptions below refer to this database.<br />
<br />
This project is been executed by [[User:Guo|guo]] and supervised by [[User:Cof|cof]].<br />
<br />
= VHDL development =<br />
VHDL development has been done with [[Tools/Mentor_HDL_Designer|HDL-Designer]] [[Tools/Versions#2011.1|2011.1]]. Make a copy of .\PTP\devel\vhdl\hdlDesigner.bat and modify the paths inside to match your system and execute it to launch the design in [[Tools/Mentor_HDL_Designer|HDL-Designer]] with all the correct paths set.<br />
== toplevel ==<br />
The toplevel of the design in the library PTP contains four major blocks. <br />
=== control ===<br />
The controlling block contains a state-machine for master mode and one for slave mode.<br />
Their tasks are to control this mode and also to command the other blocks. In master mode the node sends a Sync message each second or upon release of button1. A slave simply reacts on incoming messages according to the PTP protocol.<br />
==== Interfaces ====<br />
* cmd out, evt in<br />
==== Commands ====<br />
The following commands are always set and hold until the reception of the corresponding event.<br />
; phy_init<br />
:This command is issued each time the mode changes between master and slave and starts the initialization process of the phyter.<br />
; phy_mstslv<br />
: This status field indicates the current mode.<br />
; tx_msg_typeec<br />
: Initiates the sending of message of the given type (sync, delayResp, delayReq) on the Ethernet port.<br />
; tx_encap_type<br />
: Chooses between UDP/IP4 or L2 mode for the message to send.<br />
==== Events ====<br />
To know what's going on in the rest of the design, the control block receives events.<br />
; phy_init_done<br />
: Issued after the execution of the phyter initialization process.<br />
; tx_send_done<br />
: Indicates that a message has been sent on the Ethernet port.<br />
; rx_irq<br />
: Informs the controlling block about the reception of a message on the Ethernet port.<br />
=== rs232 ===<br />
The RS232 interface is not really needed for the PTP functionality, but serves as controlling and observation interface.<br />
There is a single internal register which defines the mst/slv mode of a device.<br />
Furthermore the phyters registers can directly be accessed.<br />
Finally all collected timestamps on the a slave are sent out over this interface.<br />
==== Interfaces ====<br />
* rs232<br />
* fifo (rx/tx)<br />
=== phyter ===<br />
This block controlls the MIIM register access of the phyter as well as it's initialization.<br />
Inside it there are three main blocks, a control block, a init action and the MIIM fifo.<br />
The control block receives the init command, controlls the reset phase of the phyter, initializes its registers and then allows the direct access to the phyter by the fifo interface. The init action block simply writes the correct values to the corresponding registers during the initialization phase. Finally the MIIM fifo sends all data presented on its input interface to the given address on the MIIM interface. All data received on the MIIM side is made available on the fifo side.<br />
==== Interfaces ====<br />
* miim<br />
* fifo (rx/tx)<br />
* cmd in, evt out<br />
=== ethernet ===<br />
This blocks sends the commanded messages on the Ethernet interface and returns the collected timestamps. Each sending of an Ethernet message is confirmed with an event. Also each reception of an Ethernet message is signaled with an event.<br />
After the reception of a delayResp message, the collected timestamps are delivered on the fifo interface. These timestamps are then, with the help of the rs232 block to a computer where they can be analyzed with the program written by Droz.<br />
==== Interfaces ====<br />
* mii<br />
* cmd in, evt out<br />
* fifo (tx)<br />
<br />
= VHDL testbench =<br />
<br />
There exists a VHDL testbench where two PTP toplevels are connected by their Ethernet interfaces. Once the toplevel_tb is loaded into ModelSim, the simulation can be executed with the command: <code>do ../../Simulation/runsim.do</code>. This will open a wave window with some important signals and also run the simulation for 16 ms.<br />
<br />
In a first step we test the initialization and the mode change feature.<br />
For the simulation, the reset time of the phyter has been reduced to 1 ms. After that time you should see 12 write access on the MDIO interfaces which configure the phyter. Both PTP toplevels are now configured in slave mode. At 1.5 ms one of the PTP toplevels is configured to be a master. You should see the write accesses on one RS232 interface. After that the reset output to the phyter of the master is again activated and at about 3.5 ms the phyter is configured in master mode again with 12 write accesses on the MDIO interface.<br />
<br />
The next step is to verify the basic PTP behavioral.<br />
At 5 ms button1 is released an this triggers a synchronization sequence. On the Ethernet interface you should see the exchange of the corresponding messages. The sync message from master to slave. Then the delayReq message from slave to master, which returns the delayResp message. This should not take more than 0.3 ms. After that the slave should send the collected timestamps on the rs232 interface.<br />
<br />
Finally two tests, a read and a write, of the rs232 access to the phyter registers are executed. At about 12.4 ms the write access is started on the master's rs232 interface. At around 13.5 this access should be sent out over the MDIO interface.<br />
The read access is started shortly after at about 14 ms and passed on the MDIO interface at about 14.7 ms.<br />
<br />
These three tests verify the basic behavior of the design. The testbench can easily be modified or extended for further specific tests.<br />
<br />
= Synthesis and PAR =<br />
<br />
The toplevel for the [[Hardware/FPGARack|FPGA Rack board]] can be found in the Library Board and is called fpga_rack. Of this design a concatenated file has to be generated at .\devel\vhdl\mine\Board\concat\concatenated.vhd. Then the prepareSynth.bat file in the same folder has to be executed. After that the [[Tools/Synopsys_Synplify|Synplify Pro]] [[Tools/Versions#2012.03_newest|2012.03]] project at .\devel\vhdl\mine\Board\synplify\fpgaRack\TBD can be launched and synthesized. The current resource utilization is around some percents and can be seen in .\doc\hes\guo\synthesis results.xlsx. Place and route is done with [[Tools/Xilinx_ISE|Xilinx ISE]] [[Tools/Versions#14.1|14.1]]. The project at .\devel\vhdl\Board\ise\PTP_fpgaRack\PTP_fpgaRack.xise contains a reference to the netlist generated with [[Tools/Synopsys_Synplify|Synplify]] and the constraints file and therefore the Generate programming file task can simply be run.<br />
<br />
= Breadboard testing =<br />
The design has been tested by loading it onto two [[Hardware/FPGARack|FPGA Rack boards]]. Then the two Ethernet ports driven by the [[Standards/Ethernet_PTP/DP83640|DP83640 phyter]] are connected together. On the computer the rs232 terminal tool ''.\PTP\devel\tools\customSerialProgram\bin\csp.exe'' has to be be launched. As next the [[Tools/QtCreator|QtCreator]] project at .\devel\tools\Qt_UART\uartassistant.pro has to be launched and compiled for release. Then both tools have to be configured to connect to one of the boards. The correct COM port has to be chosen and the baudrate to be set to 9600 baud. In the commands list on the right of the CSP tool double-click on the line below the line <code>= Set as master</code>. With the commands <code>reg y\nwr 0001 FFFF\nreg n</code> this node will be configured as master. Once you see light up LED1 on the [[Hardware/FPGARack|FPGA Rack boards]] the reinitialization of the [[Standards/Ethernet_PTP/DP83640|phyter]] is finished. If not yet done, the connection in the UARTassistant can be enabled. Now you should see there a long line of numbers appear each second. These are the collected timestamps from the slave. Once you feel that you have accumulated enough timestamps, close the connection on the UARTassistant and open the ''.csv'' file that has been generated at the same location where you compiled the UARTassistant executable. If you open it with a spreadsheet office tool, you should see the different timestamps in separated columns as well as a column with the calculated delay.<br />
<br />
Like in the simulation, all basic functions of the design are verified. More detailed tested or debugging however is not so easy to achieve.<br />
<br />
= Limitations, Bugs, Recommendations =<br />
There are some features that are already implemented but not activated or verified.<br />
* On incoming messages only the messageType field is used to detect the messsage type. A mechanism to verify the other fields has been implemented but never been tested.<br />
* There seems to be a problem with the DR_INSERT bit in the PTP_TXCFG0 register of the phyter. As soon as it is set, the received timestamp t1 in sync messages is a constant value. This means we always receive the same value. When DR_INSERT is disabled, t1 is received correctly. But then t3 is not included in the delay_resp message and should be fetched from the phyter's registers. This has not been tried yet.<br />
* We had quite some problems with the communication between the FPGA and the phyter. That's one reason why we moved from the old phyter board to the FPGArack. As we never verified on the FPGArack if the communication between FPGA and phyter also works at other speeds, we recommend to leave it's frequency as is.</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Hardware/FPGARackDebugHardware/FPGARackDebug2014-01-27T14:08:46Z<p>Admin uit: </p>
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<div>{{TOC right}}<br />
<br />
This boards allows to Debug easily the VME bus. All signals can be connected directly with the Agilent E5385A Probe to the [[Inventory/Measurement/LogicAnalyzer#Agilent_16803A|Agilent 16803A Logic Analyzer]]<br />
<br />
[[File:Agilent-e5385a.jpg|200px|Agilent E5385A Probe]] [[File:Agilent 16803A.jpg|250px]]<br />
<br />
With the help of 2 Agilent Probes almost all (4x16=64Pins) necessary signal can be connected the the Analyzer.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || Debug Board || Schematic || Description<br />
|-<br />
| V1.0 || [[File:FPGARack_Debug_Board_v1_0.jpg|200px|FPGA Rack Debug Board V1.0]] || [[Media:FPGA_Rack_Debug_Schematic.pdf|FPGA Rack Debug v1.0 Schematic PDF]] || Debug Board. Note that the '''connector is mounted in reverse''' because of PCAD Library problems<br />
|-<br />
|}<br />
<br />
The complete VME bus configuration is already stored within the [[Inventory/Measurement/LogicAnalyzer#Agilent_16803A|Agilent 16803A Logic Analyzer]]. In order to use it connect the Agilent E5385A Probes as shown below and load the following configuration: ''C:\Documents and Settings\analyser\My Documents\Agilent Tehcnologies\Logic Analyzer\Config Files\BasMI_HVME.ala''<br />
<br />
[[File:FPGARack_Debug_Board_connected.jpg|500px|FPGA Rack Debug Board ConnectedV1.0]]<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]] [[Category:VME]]</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/Hardware/FPGARackDebugHardware/FPGARackDebug2014-01-27T14:03:50Z<p>Admin uit: </p>
<hr />
<div>{{TOC right}}<br />
<br />
This boards allows to Debug easily the VME bus. All signals can be connected directly with the Agilent E5385A Probe to the [[Inventory/Measurement/LogicAnalyzer#Agilent_16803A|Agilent 16803A Logic Analyzer]]<br />
<br />
[[File:Agilent-e5385a.jpg|200px|Agilent E5385A Probe]] [[File:Agilent 16803A.jpg|250px]]<br />
<br />
With the help of 2 Agilent Probes almost all (4x16=64Pins) necessary signal can be connected the the Analyzer.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || Debug Board || Schematic || Description<br />
|-<br />
| V1.0 || [[File:FPGARack_Debug_Board_v1_0.jpg|200px|FPGA Rack Debug Board V1.0]] || [[Media:FPGA_Rack_Debug_Schematic.pdf|FPGA Rack Debug v1.0 Schematic PDF]] || Debug Board. Note that the '''connector is mounted in reverse''' because of PCAD Library problems<br />
|-<br />
|}<br />
<br />
The complete VME bus configuration is already stored within the [[Inventory/Measurement/LogicAnalyzer#Agilent_16803A|Agilent 16803A Logic Analyzer]]. In order to use it connect the Agilent E5385A Probes as follows:<br />
<br />
[[File:FPGARack_Debug_Board_connected.jpg|500px|FPGA Rack Debug Board ConnectedV1.0]]<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]] [[Category:VME]]</div>Admin uithttps://wiki.hevs.ch/uit/index.php5/File:FPGARack_Debug_Board_connected.jpgFile:FPGARack Debug Board connected.jpg2014-01-27T14:03:27Z<p>Admin uit: </p>
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