################################################################### ## Author : Zahno Silvan ## Email : silvan.zahno@hevs.ch or zahno.silvan@gmail.com ## Description : With this tcl script all vhdl source files should ## : be compiled with Modelsim 6.6 ################################################################### set text "###################################################################" set text "## Start Compilation Script comp.do" set text "###################################################################" ################################################################### ##---- Specify variables set text "###################################################################" set text "##---- Specify variables" ##-- Project path variables set Path d:/Workspaces/Eclipse/Projectname set compPath $Path/04_simulation set workPath $Path/04_simulation/work ##-- VHDL source Paths set srcVHDLPath $Path/01_design/ set srcToplPath $Path/01_design/top set srcTbPath $Path/01_design/testbench set srcMicroblazePath $Path/01_design/microblaze ##-- external Libraries Paths set srcLibIpcorePath $Path/02_libraries/ip_core_xilinx_v5 set srcLibMicroblazePath $Path/02_libraries/lib_microblaze_v5_ise11_1 set srcLibXilinxPath $Path/02_libraries/simlib_xilinx_v5 ##-- change directory cd $compPath ################################################################### ##---- 1. Creating working library set text "###################################################################" set text "##---- 1. Creating working library" ##-- Create work lib vlib $workPath ##-- Mapping work lib vmap work $workPath ################################################################### ##---- 2. Compile additional Xilinx Libaries set text "###################################################################" set text "##---- 2. Compile additional Xilinx Libaries" ##-- Lib UNISIM set text "##-- UNISIM" vmap unisim $srcLibXilinxPath/unisim ##-- Lib Microblaze v7.20a set text "##-- Microblaze v7.20a" vmap microblaze_v7_20_a $srcLibXilinxPath/edk/microblaze_v7_20_a ##-- Lib lmb ram if cntlr v2.10b set text "##-- lmb ram if cntlr v2.10b" vmap lmb_bram_if_cntlr_v2_10_b $srcLibXilinxPath/edk/lmb_bram_if_cntlr_v2_10_b ##-- Lib lmb v10 v1.00a set text "##-- lmb v10 v1.00a" vmap lmb_v10_v1_00_a $srcLibXilinxPath/edk/lmb_v10_v1_00_a ##-- Lib XilinxCoreLib set text "##-- XilinxCoreLib" vmap xilinxcorelib $srcLibXilinxPath/xilinxcorelib/ ################################################################### ##---- 3. Compile the Design set text "###################################################################" set text "##---- 3. Compile the Design" ##-- Microblaze vcom -work $workPath $srcLibMicroblazePath/microblaze_0_wrapper.vhd $srcLibMicroblazePath/ilmb_cntlr_wrapper.vhd $srcLibMicroblazePath/ilmb_wrapper.vhd $srcLibMicroblazePath/dlmb_cntlr_wrapper.vhd $srcLibMicroblazePath/dlmb_wrapper.vhd vcom -work $workPath $srcMicroblazePath/microblaze_wrapper.vhd $srcMicroblazePath/ILMB_emulator_wrapper.vhd $srcMicroblazePath/DLMB_emulator_wrapper.vhd $srcMicroblazePath/microblaze_system_wrapper.vhd ##-- RAM vcom -work $workPath $srcLibIpcorePath/blk_mem_xilinx_D40_A10_v5_v3_1.vhd ##-- My custom TL blocs vcom -work $workPath $srcVHDLPath/counter.vhd ##-- Toplevel vcom -work $workPath $srcToplPath/toplevel.vhd ##-- Testbench vcom -work $workPath $srcTbPath/tester.vhd $srcTbPath/ram_filler.vhd $srcTbPath/testbench.vhd set text "###################################################################" set text "## END OF COMPILATION" set text "###################################################################"