File:FPGA Full v2 0.jpg
From UIT
Size of this preview: 800 × 548 pixels. Other resolutions: 320 × 219 pixels | 640 × 438 pixels | 1,024 × 701 pixels | 1,280 × 877 pixels.
Full resolution (1,600 × 1,096 pixels, file size: 139 KB, MIME type: image/jpeg)
HES-SO//VS FPGA EBS V2.0 with Xilinx XC3S500E
File history
Click on a date/time to view the file as it appeared at that time.
Date/Time | Thumbnail | Dimensions | User | Comment | |
---|---|---|---|---|---|
current | 11:03, 8 March 2012 | 1,600 × 1,096 (139 KB) | Zas (Talk | contribs) | (HES-SO//VS FPGA EBS V2.0 with Xilinx XC3S500E) |
- Edit this file using an external application (See the setup instructions for more information)
File usage
The following 2 pages link to this file: