Talk:Standards/HEI 'VME' Backplane Bus

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  • VME - Critical : Write error indication to master (latency implications...)
  • VME - Critical : Wait cycles... or not ?
  • VME - Note : Data parity -> Hamming
  • VME - Critical : CPU/FPGA Side Interface ?
  • ETH - Note : Ethernet communication TTP (Trivial Transmission Protocol) or Adele register based
  • ETH - Critical : Fix bug Ethernet (RAM full, CRC error)
  • ETH - Note : RAM - FIFO thing

Prefinal version of HEVs VME bus

The command/control bits will have their name changed soon... Implementation : In progress.

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