Components/IP/Ethernet/MII to RAM

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The MII to RAM IP core interfaces the FPGA to a Media Independent Interface (MII) physical interface circuit (PHY). The core receives incoming frames and stores them in a dual port RAM. It also reads data from a second dual port RAM and sends it to the MII.

MII receiver

The MII receiver transfers Ethernet frames from the MII interface to a dual port RAM. Frames are written consecutively in the RAM and wrap around from the end of the memory to its beginning when necessary.

At the start of a new frame, a first memory word stores status bits and the frame length. Status bits fill the word MSBs and are

  • new frame available
  • RAM full
  • data error as given by the MII RXERR
  • CRC error

The circuit reading the dual port RAM can read its content in any order. It has to read the first frame word until the MSB, indicating that a new frame is available, switches to '1'. It can then read the frame length in the same word's LSBs, process the frame and then jump to the next frame start address, as calculated from the current frame base address and the frame length.

The frame's first word is given as:

n-1 n-2 : n-2-e+1  ...  m-1 : 0
frame valid error flags frame length in bytes

where:

  • n is the RAM width (typically 16)
  • e is the number of possible error flags (3)
  • m is the number of bits for counting the frame length in terms of bytes (typically 11)

An Ethernet frame can be 1522 (5F2h) bytes long, so the byte length count requires 11 bits.

The circuit reading the dual port RAM not only has to specify the read address address but also a base address which usually is the start of the frame currently being processed. If the receiver has wrapped around and would have to write data over the base address, it will cancel filling the current frame into the RAM and write a ramFull error flag in the first frame word.

When an error occurs, the corresponding flag is set and the frame length is set to 0 in order to allow the reader to jump to the next RAM word which is the next frame's first word.

This circuit works in a separate clock domain and is clocked by the MII RXCLK.

MII transmitter

The MII transmitter transfers Ethernet frames from the dual port RAM to the MII interface. Its behavior is quite similar to the emitter's.

The circuit writing the dual port RAM first has to write a '0' bit in the frame's first word MSB. It then can write frame content in any order into the memory. Once it has written the complete frame content, it writes the frame's first word with a '1' in the MSB and the frame length in the LSBs. Of course, the first memory word of the following frame should be initialized with a '0' in the MSB.

The frame's first word is given as:

n-1  ...  m+l-1 : l l-1 : 0
frame valid frame length in words number of valid bytes in last word mod l
frame valid frame length in bytes

where:

  • n is the RAM width (typically 16)
  • m is the number of bits for counting the frame length in terms of memory words (typically 10)
  • l is the number of bits for counting the bytes inside a memory word (typically 1)

In other words, m+l is the number of bits for counting the frame length in terms of bytes (typically 11).

This circuit works in a separate clock domain and is clocked by the MII TXCLK.

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