Components/IP/NanoBlaze

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The NanoBlaze is a grow-up of the Xilinx PicoBlaze microprocessor, hence the name. The PicoBlaze is a simple, orthogonal RISC Von Neumann processor which has raised a large interest and pushed developers to design several device independant variants.

This processor is used in our embedded systems course lab, together with an I/O space to AHB-Lite adapter. It processes each instruction, except for the jumps, within a single clock period.

The interrupt logic has not been implemented yet.

Component

NanoBlaze.png

The figure on the right shows the processor's inputs and outputs.

Generics

Various sizes can be defined with the help of generic parameters:

  • registerBitNb defines the data bit width
  • registerAddressBitNb allows to choose the number of internal registers
  • programCounterBitNb allows to cope with different program lengths
  • stackPointerBitNb adapts to various nesting depths of the subroutines
  • scratchPadAddressBitNb allows to manage the size of the scratchpad
  • addressBitNb defines the size of the I/O space

With scratchPadAddressBitNb = 0, the scratchpad is not implemented physically.

Speed

Contrarily to the PicoBlaze, the NanoBlaze executes every instruction within a single clock cycle. This design choice reduces the maximal operating speed compared to the original 2-cycle processor. However, an additional en input allows to have it work at half the clock rate and so catch up the performance of the original processor, as long as the synthesis tool allows to do so (to be verified). Dividing the operating frequency by a factor greater than 2 allows the NanoBlaze to work in systems working at even higher frequencies without requiring to split a design into multiple clock domains.

Synchronous BlockRam delay

The NanoBlaze's instruction ROM is designed to be mapped as a Block RAM. Due to this mapping, the instructions are provided delayed by one clock period compared to the program counter. With this, when a branch condition is met, the processor will anyway have received the instruction of the next memory location. Obviously, that instruction will not be executed, and this means that every successful branch requires two clock cycles.

Assembler

The NanoBlaze has an assembler written in PERL which thus runs on any operating system. In our labs, the assembler is integrated in the Mentor HDL Designer environment.

The VHDL processor code includes a disassembler VHDL process which translates the current instruction in the form of a string. This string can be displayed in the simulator for debugging purpose. The corresponding VHDL code is commented out for synthesis via the pragma translate_off clause.

Instruction set

The following table shows the instruction set in the case of an 8 bit processor with 16 registers and 10 program address bits:

instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 function
LOAD sX, kk 00000 0 sX address kk value loads constant kk into register sX
LOAD sX, (sY) 1 sX address sY addr - loads register sY into register sX
INPUT sX, kk 00010 0 sX address kk value loads I/O value at address kk to register sX
INPUT sX, (sY) 1 sX address sY addr - loads I/O value at address sY to register sX
FETCH sX, kk 00011 0 sX address kk value loads scratchpad value at address kk to register sX
FETCH sX, (sY) 1 sX address sY addr - loads scratchpad value at address sY to register sX
AND sX, kk 00101 0 sX address kk value applies bitwise AND of constant kk pattern to register sX
AND sX, sY 1 sX address sY addr - applies bitwise AND of register sY pattern to register sX
OR sX, kk 00110 0 sX address kk value applies bitwise OR of constant kk pattern to register sX
OR sX, sY 1 sX address sY addr - applies bitwise OR of register sY pattern to register sX
XOR sX, kk 00111 0 sX address kk value applies bitwise XOR of constant kk pattern to register sX
XOR sX, sY 1 sX address sY addr - applies bitwise XOR of register sY pattern to register sX
TEST sX, kk 01001 0 sX address kk value applies bitwise AND between constant kk and register sX, only updates C and Z flags
TEST sX, sY 1 sX address sY addr - applies bitwise AND between register sY and register sX, only updates C and Z flags
COMPARE sX, kk 01010 0 sX address kk value subtracts constant kk from register sX, only updates C and Z flags
COMPARE sX, sY 1 sX address sY addr - subtracts register sY from register sX, only updates C and Z flags
ADD sX, kk 01100 0 sX address kk value adds constant kk to register sX
ADD sX, sY 1 sX address sY addr - adds register sY to register sX
ADDCY sX, kk 01101 0 sX address kk value adds constant kk and carry bit to register sX
ADDCY sX, sY 1 sX address sY addr - adds register sY and carry bit to register sX
SUB sX, kk 01110 0 sX address kk value subtracts constant kk from register sX
SUB sX, sY 1 sX address sY addr - subtracts register sY from register sX
SUBCY sX, kk 01111 0 sX address kk value subtracts constant kk and carry bit from register sX
SUBCY sX, sY 1 sX address sY addr - subtracts register sY and carry bit from register sX
SLA sX 10000 - sX address - 0000 shifts register sX to the left, C flag goes to LSB
RL sX - sX address - 0010 rotates register sX to the left, LSB goes to LSB
SLX sX - sX address - 0100 shifts register sX to the left, LSB remains in LSB
SL0 sX - sX address - 0110 shifts register sX to the left, LSB set to 0
SL1 sX - sX address - 0111 shifts register sX to the left, LSB set to 1
SRA sX - sX address - 1000 shifts register sX to the right, C flag goes to MSB
SRX sX - sX address - 1010 shift register sX to the right, MSB remains in MSB
RR sX - sX address - 1100 rotates register sX to the right, LSB goes to MSB
SR0 sX - sX address - 1110 shifts register sX to the right, LSB set to 0
SR1 sX - sX address - 1111 shifts register sX to the right, LSB set to 1
OUTPUT sX, kk 10110 0 sX address kk value sends register sX to I/O at address kk
OUTPUT sX, (sY) 1 sX address sY addr - sends register sX to I/O at address sY
STORE sX, kk 10111 0 sX address kk value sends register sX to scratchpad at address kk
STORE sX, (sY) 1 sX address sY addr - sends register sX to scratchpad at address sY
RETURN 10101 0 - - returns from function call
RETURN Z 1 00 - returns from function call if zero flag is set
RETURN NZ 01 - returns from function call if zero flag is not set
RETURN C 10 - returns from function call if carry flag is set
RETURN NC 11 - returns from function call if carry flag is not set
CALL addr 11000 0 - program address calls function at address
CALL Z addr 1 00 program address calls function at address if zero flag is set
CALL NZ addr 01 program address calls function at address if zero flag is not set
CALL C addr 10 program address calls function at address if carry flag is set
CALL NC addr 11 program address calls function at address if carry flag is not set
JUMP addr 11010 0 - program address jumps to address
JUMP Z addr 1 00 program address jumps to address if zero flag is set
JUMP NZ addr 01 program address jumps to address if zero flag is not set
JUMP C addr 10 program address jumps to address if carry flag is set
JUMP NC addr 11 program address jumps to address if carry flag is not set
RETURNI DISABLE 11100 - 0 return from interrupt, disable further interrupts (not implemented yet)
RETURNI ENABLE - 1 return from interrupt, enable further interrupts (not implemented yet)
DISABLE INTERRUPT 11110 - 0 disable interrupts (not implemented yet)
ENABLE INTERRUPT - 1 enable interrupts (not implemented yet)

The length of the instruction word is automatically adapted to cope with the different generic values associated to the component.

Sources

This IP is found in the HEVs EDA Repository: svn: https://repos.hevs.ch/svn/eda/

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