Hardware/CubeSat Gumstix/camera connector

Connector

The connector layout is:

connector pin	signal	FPGA pin	function
1	3.3 V	power supply
2	GND
3	TxD / SCLK	A4	RS232 / I2C control
4	RxD / SDA	B10
5	Frame valid / VSync	A5	frame control
6	Line valid / HRef	C5
7	Data valid	B6
8	Pixel clock	A10
9	D0	A6	frame data
10	D1	D6
11	D2	A7
12	D3	C6
13	D4	B8
14	D5	C7
15	D6	A8
16	D7	D8
17	D8	A9
18	D9	C8
19	D10	A13
20	D11	C9
21	CC1 / ExtSync	A14	camera control
22	CC2 / XCLK	C14
23	CC3 / Reset	B14
24	CC4 / PowerDn	D14

Camera modules

The connector is meant for use with different camera modules.

OV7670

The OV7670 camera module has:

• selectable resolutions comprising VGA, CIF and their subsizes
• 16 bit RGB, YUV or Bayer raw data
• an I2C control interface

Timing generation

The camera module receives a master clock signal: XCLK. This clock signal can be multiplied by 1, 4, 6 or 8 by a PLL (DBLV[7:6] at 6B_h). The resulting frequency can be divided by an even number ( 2*(CLKRC[5:0]+1), set at 11_h ). This provides the reference clock for the image acquisition.

The acquired image can be downsampled by a factor of 2, 4 or 8 (SCALING_PCLK_DIV[3:0] at 73_h). After this, a digital zoom out can be applied with a factor of 1 to 2 separately in the horizontal (REG74[6:0] at 74_h) and vertical (REG75[6:0] at 75_h) directions. These operations can be enabled or disabled (COM3[3:2] at 0C_h).

From these, the video control signals are generated:

• VSYNC: vertical sync. with programmable polarity
• HREF: enable signal for reading, with programmable polarity
• PCLK: pixel clock

Configuration

The configuration is made via an OmniVision Serial Camera Control Bus (OSCCB), which greatly corresponds to an I2C interface.

The write address is 42_h, the read address 43_h.

References

A VHDL design example provides a good understanding of the camera system.

Photonfocus

Foreseen: OEM-D1024E-160-LC, RS232 control