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A short description of the FPGA-EBS board is found on the ISI Project Page:
[https://www.hevs.ch/en/rad-instituts/institute-of-systems-engineering/projects/fpga-board-1897 en],
[https://www.hevs.ch/fr/rad-instituts/institut-systemes-industriels/projets/fpga-board-1897 fr].

= Board families =

There are several versions of FPGA EBS Boards.
The [[Hardware/Stock_FPGA-EBS|stock]] can be verified and updated on-line.

{|class=wikitable
|- 
! Type || FPGA-EBS Full board || FPGA-EBS Student board || FPGA-EBS Mezzanine || Schematic || UCF || Description
|-
| V2.2 || None || [[File:FPGA-EBS_student_v2-2.png|200px|FPGA EBS Student Version V2.2]] [[Hardware/Stock_FPGA-EBS#FPGA-EBS_V2.2|boards 40-70]]|| None || [[Media:FPGA_EBS_v2_2_schematics.pdf|PDF]] || [[Media:FPGA_EBS_v2_xc3s500e.ucf|XC3S500e]] || Adds some bugfixes to the FPGA-EBS and has only been produced as student version with a Xilinx ''XC3S500E'' FPGA and a ''xcf04s'' Xilinx Platform Flash for persistent configuration.
|-
| V2.1 || [[File:FPGA_Full_v2_1.jpg|200px|FPGA EBS V2.1]]  [[Hardware/Stock_FPGA-EBS#Full|boards 30-35]] || [[File:FPGA_Student_v2_1.jpg|200px|FPGA EBS Student Version V2.1]] [[Hardware/Stock_FPGA-EBS#Student_2|boards 11-17]]|| [[File:FPGA_Mezza_v2_1.jpg|115px|FPGA EBS Mezza V2.1]] [[Hardware/Stock_FPGA-EBS#Mezzanine|boards 40-41]] || [[Media:FPGA_EBS_v2_1_schematics.pdf|PDF]] ||  [[Media:FPGA_EBS_v2_xc3s1200e.ucf|XC3S1200e]] <br> [[Media:FPGA_EBS_v2_xc3s500e.ucf|XC3S500e]] || Improved second version of FPGA-EBS comes with a Xilinx ''XC3S500E'' or a ''XC3S1200E''. Note that there is a different UCF Pin constraining file depending on the FPGA type. Furthermore there is a ''xcf04s'' Xilinx Platform Flash for persistent configuration.
|-
| V2.0 || [[File:FPGA_Full_v2_0.jpg|200px|FPGA EBS V2.0]] [[Hardware/Stock_FPGA-EBS#Full_2|boards 21-28]] || [[File:FPGA_Student_v2_0.jpg|200px|FPGA EBS Student Version V2.0]] [[Hardware/Stock_FPGA-EBS#Student_3|boards 1-8]] || None ||[[Media:FPGA_EBS_v2_0_schematics.pdf|PDF]] ||  [[Media:FPGA_EBS_v2_xc3s500e.ucf|XC3S500e]]  || Second FPGA-EBS Version comes with a Xilinx XC3S500E
|-
| V1.0 || [[File:FPGA_Full_v1_0.jpg|200px|FPGA EBS V1.0]]  [[Hardware/Stock_FPGA-EBS#Full_3|boards 1-3]] || [[File:FPGA_Student_v1_0.jpg|200px|FPGA EBS Student Version V1.0]]  [[Hardware/Stock_FPGA-EBS#Student_4|boards 1-8]] || [[File:FPGA_Mezza_v1_0.jpg|115px|FPGA EBS Mezza Version V1.0]]  [[Hardware/Stock_FPGA-EBS#Mezzanine_2|boards 1-15]] || [[Media:FPGA_EBS_v1_0_schematics.pdf|PDF]] || Not available ||First FPGA-EBS Version comes with a Xilinx XC2S150 or XC2S250 FPGA. <br> '''Please note that Spartan 2 is no longer supported by Xilinx, ISE Version <= 9.2i has to be used'''
|-
|}

A VHDL test code with the default UCF Files can be found at the EDA SVN Reopsitory
* https://repos.hevs.ch/svn/eda/VHDL

= Power Budget =

The [http://www.ti.com/product/tps75003 TPS750003 Power Management IC] provides up to 3A. The whole EBS board consumes 0.17A without any design loaded into the FPGA.

= UCF Pin Differences =
On the FPGA-EBS v2.X Boards, you can find two different FPGA Spartan3 Chips.

'''There are 3 Pin differences''' between Boards with XC3S500E and XC3S1200E.

{|class=wikitable
|- 
! Pin Function      || Pin on XC3S500E || Pin on XC3S1200E
|-
| ParallelPort2(16) || F4              || E6
|-
| MezzanineData(9)  || E17             || E3
|-
| sdCke             || P15             || E4
|-
|}

= Changes between FPGA-EBS V2.0 and V2.1 =
There are some other changes made in the Ethernet part of those boards. Several bugs were changes and corrected.

* TCT and RCT Pins of the Ethernetconnector were strapped to 3.3V, and decoupled with Capacitors (C59 & C104)
* Serial Capacitors on the RX+ and RX- lines were replaced by 0Ohm Resistors (R61 & R63)
* Proper Reset circuit for the Ethernetphy is put on place (D13, D14, R62 & C108)

= Configuration =
This board can be configured in 2 ways:
* directly
* via the onboard Flash memory

For more details see [[Hardware/FPGAEBS/Configuration|FPGA-EBS Configuration]]

= Stock =

The [[Hardware/Stock_FPGA-EBS|stock]] comprises:
* V 2.2 : 11 minimal
* V 2.1 : 6 full, 7 student
* V 2.0 : 6 full, 7 student

[[Category:Hardware]]
[[Category:FPGAEBS]]
[[Category:ParallelPort]]
[[Category:RS232]]