Hardware/FPGARackEdison
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| − | The board is compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEVs_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]] | + | The board comprises a controller FPGA and Linux microprocessor systems. |
| + | It is tailored for low-power, real-time image processing. | ||
| + | The board is compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEVs_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]]. | ||
= Hardware features = | = Hardware features = | ||
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== Intel Edison compute modules == | == Intel Edison compute modules == | ||
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* a SPI link | * a SPI link | ||
* an [http://www.ftdichip.com/Products/ICs/FT232H.htm USB FIFO] circuit | * an [http://www.ftdichip.com/Products/ICs/FT232H.htm USB FIFO] circuit | ||
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| + | Additionally, the FPGA connects to a general purpose 24-pin connector and to a VME backplane connector. | ||
| + | The 24-pin connector is foreseen for interfacing a camera. | ||
== VME connection == | == VME connection == | ||
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* parallel bus: A7 ÷ A0, D15 ÷ D0, en, wr, ready, freeze, mode | * parallel bus: A7 ÷ A0, D15 ÷ D0, en, wr, ready, freeze, mode | ||
* SPI bus | * SPI bus | ||
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= Programmation = | = Programmation = | ||
Revision as of 09:10, 26 November 2015
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Board Overview
| Type | FPGA Rack | Schematic | User constraints file | Description |
|---|---|---|---|---|
| V1.0 | FPGA Rack Edison v1.0 | FPGA-Rack Edison v1.0 Schematic PDF | TBD | 5 Intel Edison Compute Modules and Microsemi AGL1000 FPGA |
The board comprises a controller FPGA and Linux microprocessor systems. It is tailored for low-power, real-time image processing. The board is compatible with the FPGA Rack Backplane for interconnecting different boards with the help of the HES-SO Backplane Bus and the HES-SO VME IP Core.
Hardware features
Intel Edison compute modules
The board can host up to 5 Intel Edison compute modules.
On-board communication
The FPGA connects to each compute module individually with:
- a serial port
- a SPI link
- an USB FIFO circuit
Additionally, the FPGA connects to a general purpose 24-pin connector and to a VME backplane connector. The 24-pin connector is foreseen for interfacing a camera.
VME connection
The VME connector at the back is compatible with the HEI Backplane Bus, making it compatible with the other HEI VME rack components. The Edison cluster board can thus be used for controlling an instrument built out of these devices.
Connected signals are:
- parallel bus: A7 ÷ A0, D15 ÷ D0, en, wr, ready, freeze, mode
- SPI bus
Programmation
TBD
