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This board, initially targeted to power the HiRADDA Core board, can be used as generic power source for many project needing multiple high current and low noise voltage sources.

Type FPGA Rack Documentation Description
Restricted access
Full documentation
Designed for HiRADDA Core.
Designed for IGOR V power input needs.
OCP limits: LDO ~1.8A, DC/DC ~7A.
Control FPGA: Atrix XC7A15/35/50T.

The HiRADDA Power set is composed of two boards :

  • Digital board (8-layer PCB)
    This is the main power board, with digital power rails and control logic.
  • Analog board (4-layer PCB)
    An extension board offering some analog power rails. Optional.


HiRADDA Power boards, unplugged, without heat sinks HiRADDA Power boards, mounted with HiRADDA Core on bottom

System overview

HiRADDA Power Overview

Power Inputs

There is 3 power sources :

  • +D6...30V for digital domain
    • Mandatory
    • Wide input voltage range
  • +A5.5V for analog/clock domain
    • Optional
    • Tested at startup and auto-powered from digital domain (filtered) if missing ( /!\ Don't connect analog after power-up /!\ )
  • -A5.5V for analog domain
    • Optional

In-rush current measures

  • Digital +D6...30V : ~150A@24V during 100us (source: 24V 8Ah LiFe battery).
    • Only the capacitance in input of the 3 DC/DC is responsible of that value (all output power rails unpowered).
    • ...so don't use fast fuses with batteries.
  • Analog/Clock : Not measured.

Power output

The boards offers some DC/DC and regulator (LDO) powered outputs.
Be careful to the max current for each power rail because some share the same parent (see overview diagram).
All power rails are equipped with overcurrent (OCP), overvoltage (OVP) and undervoltage (UVP) measures IC for protection (see 'System behavior').

Digital board

  • 2x positive filtered DC/DC 10A
  • 4x positive filtered LDO 3A (all share a parent DC/DC +D3.3V)

Analog board

  • 7x positive filtered LDO 3A (some share a parent LDO +A3.6V)
  • 1x negative filtered LDO 1.5A

System thermal dissipation

The thermal dissipation is very depending on the user application and power input. It can be easily calculated according to the 'Overview diagram'.
Each board is equipped with a full surface heat sink. A forced air flow may be recommended in closed area use, like racks.

System behavior

The following behavior is based on the SpinalHDL code "xADDAPower" present on SVN "xADDACore".

The control FPGA embedded in the digital board drives and monitors the power boards. Its boot is quite instantaneous (<200ms) (the DCDCs/regulators won't drive in case of boot failure).

Power-up sequence

1) Power up sequentially all regulators according to the defined sequence.
2) Log the good power-up event in the FRAM (optional).

Shutdown sequence

1a) Power board requested shutdown
If communication available with the core board :

  • > Informs the core board of the shutdown request.
  • < The core board acknowledge the request (if timeout, then go to point 2), eventually with a grace period request.
  • < If grace period request, the core send a shutdown confirm when ready.

1b) Core board requested shutdown :

  • < The core board send the shutdown request.

2) Shutdown sequentially all regulators according to the defined sequence.
3) Log the good shutdown event in the FRAM (optional).

DC/DC frequency Control

During power on state, the core board can modify the DC/DCs work frequency/phase at any time.

M/FRAM log

The digital board can be equipped either with a small serial magnetoresistive or ferroelectric RAM (non volatile).
During power on state, the core board can read back the FRAM.


1) All powers rails off instantaneously. The incident detail is shown on the front LEDs.
2) Log the event with details in the M/FRAM.

Changelog / Known issues

V1.00 'IGOR V'

  • S1B : Illuminated switch [Non critical issue : Correction needed at user convenience]
    Cathode of LEDs S1B should be connected on +F3.3V for light the switch.
  • U19 : Voltage level shifter for +A5.0V power rail enable (U20) [Non critical issue : Normally no correction needed, but recommended]
    U19 is half decoupled and C155 routed far away the IC. Adding two 100nF decoupling capacitors near U19 recommended.
  • Overlay layouts [Information]
    There is some unwanted texts/lines on overlay layout and some power rails denomination are wrong, according to HiRADDA Core V1.00 usage.
  • Reverse voltage protections [Information]
    Theses are successfully tested on early soldering stage (with board near-empty) and not on the final design for safety reasons (excepted -A5.5V : OK).
    But in any case, please try to avoid to use them, particularly with voltage >>6V ;-) ...or correct this document if you succeeded... :-P
  • Digital inrush current [Information]
    ...due to DC/DC input capacitors. Reduce it a little... ;-)

Contacts / Collaborators

This board was initially targeted for Dominique Roggo's IGOR V and Joseph Moerschell's projects.

Project managers :

Main developper (Design/Schematics) :

PCB routing :

PCB components soldering :

Additionnal checks on schematics :

VHDL/SpinalHDL dev & physical tests :

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