Hardware/FPGARackHiRADDAV1

From UIT
Revision as of 17:04, 27 January 2016 by Alexandr.ganchinh (Talk | contribs)
Jump to: navigation, search

Contents

The main purpose behind this board is to have a powerful development FPGA board specialized in high-resolution data acquisition and processing.

Type FPGA Rack Documentation Description
V1.00
Restricted access
Full documentation
Kintex7 XC7K160T-xFFG676

The HiRADDA set is composed of two or more boards :

  • HiRADDA Core
  • HiRADDA Power
  • n x user extension boards

HiRADDA is compatible with the FPGA Rack Backplane for interconnecting different boards with the help of the HVME16/32 version of the HES-SO Backplane Bus and the HES-SO VME IP Core. Additional specific hardware can be connected to HiRADDA as stackable mezzanine card.

HiRADDA embeds multiples memories for different usecases : DDR3 SDRAM for high speed sampling/processing, FLASH for non-volatile data (including softcores code) and Ferroelectric/Magnetoresistive RAM for non-volatile user parameters/logs.

HiRADDA Core V1.00 PCB 3D View

Core features

Main board

This 160x100mm (Eurocard) 16 layers PCB contains the following parts :

  • 2x A/D 24bits 4MSPS (Ti ADS1675) with 2 analog paths :
    • Direct (differential)
    • Through operational amplifier (single/differential)
  • 1x D/A 16bits 500MSPS (Maxim MAX5888), current source, with 1 analog path :
    • Direct (differential)
  • 1x Xilinx Kintex7 XC7K160T-xFFG676 (XC7K70T/XC7K325T compatible)
    • 162.24k logic cells, 25.35k slices (max 2.188Mb of distributed RAM)
    • 11.7Mb block RAM (650x18Kb / 325x36Kb)
    • 600 DSP Slices
    • GTX I/Os
  • 1x Low-jitter clock generator/distributor for ADC/DAC/DDR3/FPGA (AD9517-4 with 1.6GHz VCO)
  • 1x 100MHz quartz for boot clock
  • 1x expansion connectors with the following FPGA banks :
    • Full HR bank 13 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 3.465V).
    • Full HP bank 33 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 1.89V).
    • Full GTX banks 115 & 116 (8x TX ,8x RX, 4x reference clocks) - for PCI-Express 8x, SATA, SFP etc... use.
  • 1x additional connector with 8 I/Os (+3.3V).
  • 1x fully isolated USB2.0<->UART interface with hardware flow control.
  • 1x additional connector with isolated 2x input and 2x output (reduce some UART functionnalities if used).
  • Various memories for work/parameters :
    • 1x 256MiB DDR3 (32M x 8banks x 8bit width)
    • 2x 32MiB Serial QuadSPI NOR Flash (one reserved for FPGA programming, bigger compatible ones available)
    • 1x 256KiB Serial SPI Ferroelectric-RAM (pin compatible Magnetoresistive-RAM can be soldered too, bigger compatible ones available)
  • 4x user RGB LEDs
  • 10x user DIL switches
  • 1x JTAG connector
  • 1x DIN41612 VME compatible connector 3x32 pins (full HVME32, 1.8V/2.5V/3.3V) with CMOS AC termination on all signal pins (default: unsoldered)

Power supply considerations

The following power rails have to be produced on the HiRADDA Power board :

  • +C2.5V (AD9517-4)
  • +C3.3V (AD9517-4)
  • -A5.0V - Optional, for AOP input range extension
  • +A1.0V - Optional, for FPGA GTX I/Os.
  • +A1.2V - Optional, for FPGA GTX I/Os.
  • +A1.8V - Optional, for FPGA GTX I/Os.
  • +A3.3V (MAX5888)
  • +A5.0V (ADS1675)
  • +D1.0V (FPGA Core)
  • +D1.5V (DDR3 SDRAM Core)
  • +D1.8V - Optional, for user I/Os
  • +D2.5V (LVDS VCXO, user I/Os)
  • +D3.0V (ADS1675)
  • +D3.3V (multiple usage, incl. user I/Os)

The following power rails are produced locally on the core board :

  • +DR0.75V (DDR3 SDRAM Core)
  • +AR2.5V (ADC)
  • +AR3.0V (ADC)

VME connector considerations

  • No power rail are connected to the VME connector.
  • The I/O bank which interfaces the VME connector can be 1.8V, 2.5V or 3.3V depending on the jumper XXX position. Be careful with other FPGA Rack boards different voltage configuration.

Programming

The FPGA on this board can be programmed in 2 ways :

  • directly through JTAG interface.
  • automatically on boot via the onboard FLASH memory. This serial FLASH can be accessed in :
    • SPI SDR x1 : ~20s boot time
    • SPI SDR x4 : ~ 5s boot time
    • SPI DDR xn is not supported.

More explanation about FLASH programming is available here.

Known issues

  • None yet.

Contacts / Collaborators

This board was initially targeted for Dominique Roggo's and Joseph Moerschell's projects.

Project manager :

Schematics/Design :

PCB routing :

Additionnal checks :

Personal tools
Namespaces
Variants
Actions
Navigation
Browse
Toolbox