Hardware/Parallelport/heb inverter

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(Dead time)
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The dead time estimation for the H-Brige has been setimated by augmenting it an monitoring the power consumption of the system.
 
The dead time estimation for the H-Brige has been setimated by augmenting it an monitoring the power consumption of the system.
 
The daead time was given by a counter clocked at 66 MHZ, but with a different number of bits for each measure.
 
The daead time was given by a counter clocked at 66 MHZ, but with a different number of bits for each measure.
3 | 860
+
{|class=wikitable
4 | 170
+
|-
5 | 70
+
! bit nb || dead time || current [mA]
6 | 70
+
|-
 +
| 3 || xxx || 860
 +
|-
 +
| 4 || xxx || 170
 +
|-
 +
| 5 || xxx || 70
 +
|-
 +
| 5 || xxx || 70
 +
|}
  
 
[[Category:Hardware]] [[Category:Parallelport]] [[Category:HEB]]
 
[[Category:Hardware]] [[Category:Parallelport]] [[Category:HEB]]

Revision as of 13:54, 17 January 2022

Contents

Inverter board

The board was designed for the ETE ELN-inverter lab.

It receives 4 PWM signals to drive an H-Bridge. The bridge is followed by an LC-lowpass and a transformer.

A sigma-delta ADC reads the LC filter output and enables to adjust the output voltage.

Version Photo Schematics Stock
V1.0 HEB-Synchro HEB-inverter Schematic PDF 16fully mounted

Dead time

The dead time estimation for the H-Brige has been setimated by augmenting it an monitoring the power consumption of the system. The daead time was given by a counter clocked at 66 MHZ, but with a different number of bits for each measure.

bit nb dead time current [mA]
3 xxx 860
4 xxx 170
5 xxx 70
5 xxx 70
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