Hardware/Parallelport/heb microphone
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(Created page with "{{TOC right}} The board was designed for the [http://wiki.hevs.ch/fsi/index.php5/SEm SEm] VHDL FSM lab. It has a beeper which can emit a [https://en.wikipedia.org/wiki/Morse...") |
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It has a beeper which can emit a [https://en.wikipedia.org/wiki/Morse_code Morse code] signal | It has a beeper which can emit a [https://en.wikipedia.org/wiki/Morse_code Morse code] signal | ||
and a microphone for receiving it. | and a microphone for receiving it. | ||
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{|class=wikitable | {|class=wikitable | ||
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| V1.1 ||[[File:Microphone.jpg |200px|HEB-microphone]] || [[Media:Microphone.pdf|HEB-microphone Schematic PDF]] || [[Hardware/Stock_PP#HEB_Synchro|10 fully mounted]] | | V1.1 ||[[File:Microphone.jpg |200px|HEB-microphone]] || [[Media:Microphone.pdf|HEB-microphone Schematic PDF]] || [[Hardware/Stock_PP#HEB_Synchro|10 fully mounted]] | ||
|} | |} | ||
+ | |||
+ | = Beeper = | ||
+ | |||
+ | The beeper is driven directly by a digital I/O line. | ||
+ | |||
+ | = Microphone = | ||
+ | |||
+ | The microphone's output is amplified and connected to an [http://www.analog.com/en/products/analog-to-digital-converters/ad7995.html ADC]. | ||
+ | The amplified signal is also triggered in order to deliver a simple digital input to the FPGA. | ||
+ | |||
+ | == Setup == | ||
+ | |||
+ | The microphone's output is quite small. | ||
+ | It is first fed to a fixed amplifier through a passive RC highpass. | ||
+ | The highpass has a cutoff frequency of ... Hz. | ||
+ | The amplifier has a gain of xxx. | ||
[[Category:Hardware]] [[Category:Parallelport]] [[Category:HEB]] | [[Category:Hardware]] [[Category:Parallelport]] [[Category:HEB]] |
Revision as of 10:52, 18 May 2018
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The board was designed for the SEm VHDL FSM lab.
It has a beeper which can emit a Morse code signal and a microphone for receiving it.
Version | Photo | Schematics | Stock |
---|---|---|---|
V1.1 | HEB-microphone Schematic PDF | 10 fully mounted |
Beeper
The beeper is driven directly by a digital I/O line.
Microphone
The microphone's output is amplified and connected to an ADC. The amplified signal is also triggered in order to deliver a simple digital input to the FPGA.
Setup
The microphone's output is quite small. It is first fed to a fixed amplifier through a passive RC highpass. The highpass has a cutoff frequency of ... Hz. The amplifier has a gain of xxx.