Hardware/Parallelport/heb synchro

(Difference between revisions)
Jump to: navigation, search
(Synchro)
Line 3: Line 3:
  
 
The board was designed for the [http://wiki.hevs.ch/ete/index.php5/Main_Page ETE] [http://wiki.hevs.ch/ete/index.php5/Synchro ELN-synchro lab].
 
The board was designed for the [http://wiki.hevs.ch/ete/index.php5/Main_Page ETE] [http://wiki.hevs.ch/ete/index.php5/Synchro ELN-synchro lab].
 +
 +
It receives 2 sinewaves: one from a 50 Hz function generator and one from the AC generator. These signals are triggered at 0 V in order to deliver logic-level signals to the FPGA.
 +
 +
The FPGA delivers a PWM output which controls a power switch. The switch then drives the DC motor.
  
 
{|class=wikitable
 
{|class=wikitable
 
|-  
 
|-  
! Version || Photo || Schematics || Stock || Description
+
! Version || Photo || Schematics || Stock
 
|-
 
|-
| V1.0 ||[[File:HEB Synchro v1.jpg|200px|HEB-Synchro]] || [[Media:heb_synchro.pdf|HEB-Synchro Schematic PDF]] || [[Stock_PP#HEB_Synchro|12 fully mounted]] || HEB Synchro
+
| V1.0 ||[[File:HEB Synchro v1.jpg|200px|HEB-Synchro]] || [[Media:heb_synchro.pdf|HEB-Synchro Schematic PDF]] || [[Stock_PP#HEB_Synchro|12 fully mounted]]
 
|}
 
|}
  
 
[[Category:Hardware]] [[Category:Parallelport]] [[Category:HEB]]
 
[[Category:Hardware]] [[Category:Parallelport]] [[Category:HEB]]

Revision as of 15:46, 16 January 2015

Contents

Synchro

The board was designed for the ETE ELN-synchro lab.

It receives 2 sinewaves: one from a 50 Hz function generator and one from the AC generator. These signals are triggered at 0 V in order to deliver logic-level signals to the FPGA.

The FPGA delivers a PWM output which controls a power switch. The switch then drives the DC motor.

Version Photo Schematics Stock
V1.0 HEB-Synchro HEB-Synchro Schematic PDF 12 fully mounted
Personal tools
Namespaces
Variants
Actions
Navigation
Browse
Toolbox