Projects/AMBAdraw
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AMBAdraw (a.k.a. AMBArchitect)
The increasing capacity of programmable logic components makes it possible to integrate more and more functions on the same chip. This increasing complexity pushes the active companies in this field to adapt their methodologies of development so that they can satisfy the needs of the market within the shortest time.
A first stage consists in re-using already developed functions. The designer of integrated logic finds many IP (Intellectual Property) cores making it possible to satisfy whole or part of these needs. However these IP cores can be very expensive, badly documented or badly adapted to a selected architecture system.
In a second stage the originators fold up themselves towards the use of standard buses in order to limit the adaptations of IP cores. They develop thus around these buses libraries of components allowing a faster integration. Let us name among the buses most largely used AMBA (ARM), WISHBONE (OpenCores) or CoreConnect (IBM). Various libraries from IP cores thus saw the day such as the GRLIB (Gaisler Research Library) based on AMBA or the library OpenCores based on WISHBONE. These libraries being for a great part in free accesses it becomes very interesting for SMEs to integrate them in their process of development. Unfortunately no tool makes it possible starting from these libraries to carry out in a convivial way (Lego-like) architecture of an integrated system taking account of the various needs for configuration for each one of the IP cores. Moreover, the use of these libraries requires a very precise knowledge of the bus used and IP cores integrated. Without this knowledge it becomes very difficult for SMEs to develop powerful logics integrated in a very short time.
The scientific objectives of the AMBArchitect project consist of:
- Setting up a graphic environment to design the architecture of a SoC (System one Chip) based on the bus AMBA and the GRLIB. This tool must allow the placement of graphic forms of the components on the bus AMBA, the introduction of the configuration parameters of the IP cores in the form of a table and finally the generation of the VHDL code of the complete SoC
- Establishing the procedure to add new components in the standard library used
- Using the developed tools to realize a simple SoC containing a LEON processor, an Ethernet interface, a UART port and logical inputs/outputs.
The economic objectives are:
- Increasing the productivity of the development teams in the field of integrated electronic design
- Turning the network ISYS into a privileged partner of the SMEs of Western Switzerland for the integrated systems development based on AMBA.
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