https://wiki.hevs.ch/uit/index.php5?title=Tools/Xilinx_ISE/UCF_ShortGuide&feed=atom&action=historyTools/Xilinx ISE/UCF ShortGuide - Revision history2024-03-29T08:40:50ZRevision history for this page on the wikiMediaWiki 1.18.1https://wiki.hevs.ch/uit/index.php5?title=Tools/Xilinx_ISE/UCF_ShortGuide&diff=375&oldid=prevZas: /* A short guide to constraints in FPGA */2012-02-15T12:01:24Z<p><span class="autocomment">A short guide to constraints in FPGA</span></p>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA. In fact, most problems with an FPGA timing occur because of three reasons:  </div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA. In fact, most problems with an FPGA timing occur because of three reasons:  </div></td></tr>
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<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div><del class="diffchange diffchange-inline">- </del>False paths</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins class="diffchange diffchange-inline"># </ins>False paths</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div><del class="diffchange diffchange-inline">- </del>Timing issues due to reading data from outside the FPGA with a clock</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins class="diffchange diffchange-inline"># </ins>Timing issues due to reading data from outside the FPGA with a clock</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div><del class="diffchange diffchange-inline">- </del>Timing issues due to outputting data to another component from the FPGA with a clock.</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins class="diffchange diffchange-inline"># </ins>Timing issues due to outputting data to another component from the FPGA with a clock.</div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>== 1. Problem A : false paths ==</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>== 1. Problem A : false paths ==</div></td></tr>
</table>Zashttps://wiki.hevs.ch/uit/index.php5?title=Tools/Xilinx_ISE/UCF_ShortGuide&diff=374&oldid=prevZas at 12:01, 15 February 20122012-02-15T12:01:00Z<p></p>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>An example of such a constraint for a UCF file is given here :</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>An example of such a constraint for a UCF file is given here :</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"><source lang='tcl'></ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>INST "broadenc_cpu_i/axi_intc_0/axi_intc_0/INTC_CORE_I/hw_intr_1" TNM = UBlaze_Interrupts;</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>INST "broadenc_cpu_i/axi_intc_0/axi_intc_0/INTC_CORE_I/hw_intr_1" TNM = UBlaze_Interrupts;</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>INST "broadenc_cpu_i/axi_intc_0/axi_intc_0/INTC_CORE_I/hw_intr_2" TNM = UBlaze_Interrupts;</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>INST "broadenc_cpu_i/axi_intc_0/axi_intc_0/INTC_CORE_I/hw_intr_2" TNM = UBlaze_Interrupts;</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>TIMESPEC TS_UBlaze_Interrupts = TO "UBlaze_Interrupts" TIG; # We don't care of timing for interrupts</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>TIMESPEC TS_UBlaze_Interrupts = TO "UBlaze_Interrupts" TIG; # We don't care of timing for interrupts</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></source></ins></div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This creates a group for two signals and then use the TIG constraint to it. If your instance</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This creates a group for two signals and then use the TIG constraint to it. If your instance</div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>you respect setup and hold times in your input register. In order to do, a simple constraint like</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>you respect setup and hold times in your input register. In order to do, a simple constraint like</div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>OFFSET = IN 4 ns VALID 8 ns BEFORE "mb_vclk";</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>OFFSET = IN 4 ns VALID 8 ns BEFORE "mb_vclk";</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></source></ins></div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>indicate that the data that are registered with the signal mb_vclk (which must be a constrained clock)</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>indicate that the data that are registered with the signal mb_vclk (which must be a constrained clock)</div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>in putting the following constraint :  </div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>in putting the following constraint :  </div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>net "ve_vclk" TNM_NET = "vdata_out";</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>net "ve_vclk" TNM_NET = "vdata_out";</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>net "ve_vy<0>" TNM_NET = "vdata_out";</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>net "ve_vy<0>" TNM_NET = "vdata_out";</div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>net "ve_vy<4>" TNM_NET = "vdata_out";</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>net "ve_vy<4>" TNM_NET = "vdata_out";</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>TIMEGRP "vdata_out" OFFSET = OUT AFTER "mb_vclk" REFERENCE_PIN "ve_vclk";</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>TIMEGRP "vdata_out" OFFSET = OUT AFTER "mb_vclk" REFERENCE_PIN "ve_vclk";</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></source></ins></div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>Those constraints have the following meaning : we group all the signals in a group "vdata_out". This</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>Those constraints have the following meaning : we group all the signals in a group "vdata_out". This</div></td></tr>
</table>Zashttps://wiki.hevs.ch/uit/index.php5?title=Tools/Xilinx_ISE/UCF_ShortGuide&diff=373&oldid=prevZas at 12:00, 15 February 20122012-02-15T12:00:09Z<p></p>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>whole group (which is output and constitues the reference for all the other signals) is ve_vclk. Note</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>whole group (which is output and constitues the reference for all the other signals) is ve_vclk. Note</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>that this pin must be included in the group.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>that this pin must be included in the group.</div></td></tr>
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</table>Zashttps://wiki.hevs.ch/uit/index.php5?title=Tools/Xilinx_ISE/UCF_ShortGuide&diff=369&oldid=prevZas: /* A short guide to constraints in FPGA */2012-02-15T11:56:33Z<p><span class="autocomment">A short guide to constraints in FPGA</span></p>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>= A short guide to constraints in FPGA =</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>= A short guide to constraints in FPGA =</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div>by Pierre-Andre Mudry 2011</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins class="diffchange diffchange-inline">'''</ins>by Pierre-Andre Mudry 2011<ins class="diffchange diffchange-inline">'''</ins></div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This small guide indicates how to resolve most timing problems / constraints inside an  </div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This small guide indicates how to resolve most timing problems / constraints inside an  </div></td></tr>
</table>Zashttps://wiki.hevs.ch/uit/index.php5?title=Tools/Xilinx_ISE/UCF_ShortGuide&diff=368&oldid=prevZas at 11:56, 15 February 20122012-02-15T11:56:06Z<p></p>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>= A short guide to constraints in FPGA =</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>= A short guide to constraints in FPGA =</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>by Pierre-Andre Mudry 2011</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>by Pierre-Andre Mudry 2011</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This small guide indicates how to resolve most timing problems / constraints inside an  </div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This small guide indicates how to resolve most timing problems / constraints inside an  </div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA. In fact, most problems with an FPGA timing occur because of three reasons:  </div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA. In fact, most problems with an FPGA timing occur because of three reasons:  </div></td></tr>
</table>Zashttps://wiki.hevs.ch/uit/index.php5?title=Tools/Xilinx_ISE/UCF_ShortGuide&diff=367&oldid=prevZas at 11:55, 15 February 20122012-02-15T11:55:56Z<p></p>
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<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>{{TOC right}}</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>{{TOC right}}</div></td></tr>
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<tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div>= A short guide to constraints in FPGA<del class="diffchange diffchange-inline">, </del>Pierre-Andre Mudry 2011 <del class="diffchange diffchange-inline">=</del></div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>= A short guide to constraints in FPGA <ins class="diffchange diffchange-inline">=</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins class="diffchange diffchange-inline">by </ins>Pierre-Andre Mudry 2011</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This small guide indicates how to resolve most timing problems / constraints inside an  </div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This small guide indicates how to resolve most timing problems / constraints inside an  </div></td></tr>
<tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA. In fact, most problems with an FPGA timing occur because of three reasons:  </div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA. In fact, most problems with an FPGA timing occur because of three reasons:  </div></td></tr>
</table>Zashttps://wiki.hevs.ch/uit/index.php5?title=Tools/Xilinx_ISE/UCF_ShortGuide&diff=366&oldid=prevZas: Created page with "{{TOC right}} = A short guide to constraints in FPGA, Pierre-Andre Mudry 2011 = This small guide indicates how to resolve most timing problems / constraints inside an FPGA. ..."2012-02-15T11:55:33Z<p>Created page with "{{TOC right}} = A short guide to constraints in FPGA, Pierre-Andre Mudry 2011 = This small guide indicates how to resolve most timing problems / constraints inside an FPGA. ..."</p>
<p><b>New page</b></p><div>{{TOC right}}<br />
<br />
= A short guide to constraints in FPGA, Pierre-Andre Mudry 2011 =<br />
This small guide indicates how to resolve most timing problems / constraints inside an <br />
FPGA. In fact, most problems with an FPGA timing occur because of three reasons: <br />
<br />
- False paths<br />
- Timing issues due to reading data from outside the FPGA with a clock<br />
- Timing issues due to outputting data to another component from the FPGA with a clock.<br />
<br />
== 1. Problem A : false paths ==<br />
A simple example for the first case is when you generate the TX line of an UART or <br />
when you consider interrupt lines in a uBlaze (for instance). In both cases, those signals are<br />
not synchronous with respect to your clock. You must then indicate that those nets<br />
are to be ignored by timing checks. In order to do it, for Xilinx FPGA you must use the TIG<br />
constraint (which stands for Timing IGnore). The only problem here is that you can't put<br />
that constraint in your VHDL file but you have to put it in the UCF file. When you have<br />
internal signals, you require to use the complete path of the net (which can be found for<br />
example by displaying the schematic of your design or with the report of the timing <br />
analyser). <br />
<br />
An example of such a constraint for a UCF file is given here :<br />
<br />
INST "broadenc_cpu_i/axi_intc_0/axi_intc_0/INTC_CORE_I/hw_intr_1" TNM = UBlaze_Interrupts;<br />
INST "broadenc_cpu_i/axi_intc_0/axi_intc_0/INTC_CORE_I/hw_intr_2" TNM = UBlaze_Interrupts;<br />
TIMESPEC TS_UBlaze_Interrupts = TO "UBlaze_Interrupts" TIG; # We don't care of timing for interrupts<br />
<br />
This creates a group for two signals and then use the TIG constraint to it. If your instance<br />
name is incorrect, the synthesis tool will complaint.<br />
<br />
== 2. Problem B : reading data from outside the FPGA ==<br />
When you read synchronous data (i.e. with an incoming clock) in an FPGA, you must be sure that<br />
you respect setup and hold times in your input register. In order to do, a simple constraint like<br />
<br />
OFFSET = IN 4 ns VALID 8 ns BEFORE "mb_vclk";<br />
<br />
indicate that the data that are registered with the signal mb_vclk (which must be a constrained clock)<br />
must comply with a setup of 4 ns and a hold time of 4 ns. By doing it like this, you won't have any<br />
problem with source synchronous systems (in which the clock are transmitted from another device with<br />
the data).<br />
<br />
== 3. Problem C: outputting synchronous data correctly with an FPGA ==<br />
When you generate data for another system in your FPGA and you also generate the clock for that system (<br />
a global clock is not shared between all elements of the system (FPGA and device) for that bus), making<br />
sure that the data are aligned with the clock and are output with correct setup and hold times consist <br />
in putting the following constraint : <br />
<br />
net "ve_vclk" TNM_NET = "vdata_out";<br />
net "ve_vy<0>" TNM_NET = "vdata_out";<br />
net "ve_vy<1>" TNM_NET = "vdata_out";<br />
net "ve_vy<2>" TNM_NET = "vdata_out";<br />
net "ve_vy<3>" TNM_NET = "vdata_out";<br />
net "ve_vy<4>" TNM_NET = "vdata_out";<br />
TIMEGRP "vdata_out" OFFSET = OUT AFTER "mb_vclk" REFERENCE_PIN "ve_vclk";<br />
<br />
Those constraints have the following meaning : we group all the signals in a group "vdata_out". This<br />
group is generated with a clock (here mb_vclk, which remains inside the FPGA) and the clock for the<br />
whole group (which is output and constitues the reference for all the other signals) is ve_vclk. Note<br />
that this pin must be included in the group.</div>Zas