HiRel/CanSat/Master FPGA
(→Connections) |
|||
Line 37: | Line 37: | ||
<!-- slave 1, power board, bottom --> | <!-- slave 1, power board, bottom --> | ||
| rowspan=8 | slave 1:<br />[[HiRel/CanSat/Slave_Power|Power]] || rowspan=4 | bottom | | rowspan=8 | slave 1:<br />[[HiRel/CanSat/Slave_Power|Power]] || rowspan=4 | bottom | ||
− | | TxD || | + | | TxD || J1.1 || 127 || in |
|- | |- | ||
− | | RxD || | + | | RxD || J1.3 || 124 || out |
|- | |- | ||
− | | LED 0 || | + | | LED 0 || J1.5 || 121 || out |
|- | |- | ||
− | | LED 1 || | + | | LED 1 || J1.7 || 118 || out |
|- | |- | ||
<!-- slave 1, power board, top --> | <!-- slave 1, power board, top --> | ||
Line 57: | Line 57: | ||
<!-- slave 2, XBee Board, bottom --> | <!-- slave 2, XBee Board, bottom --> | ||
| rowspan=8 | slave 2:<br />[[HiRel/CanSat/Slave_XBee|Radio]] || rowspan=4 | bottom | | rowspan=8 | slave 2:<br />[[HiRel/CanSat/Slave_XBee|Radio]] || rowspan=4 | bottom | ||
− | | RxD || | + | | RxD || J1.2 || 126 || out |
|- | |- | ||
− | | TxD || | + | | TxD || J1.4 || 123 || in |
|- | |- | ||
− | | reset_n || | + | | reset_n || J1.6 || 119 || out |
|- | |- | ||
− | | sleep request || | + | | sleep request || J1.8 || 117 || out |
|- | |- | ||
<!-- slave 2, Radio board, top --> | <!-- slave 2, Radio board, top --> | ||
Line 77: | Line 77: | ||
<!-- slave 3, COM board, bottom --> | <!-- slave 3, COM board, bottom --> | ||
| rowspan=8 | slave 3:<br />[[HiRel/CanSat/Slave_Gumstix|Computer On Module]] || rowspan=4 | bottom | | rowspan=8 | slave 3:<br />[[HiRel/CanSat/Slave_Gumstix|Computer On Module]] || rowspan=4 | bottom | ||
− | | RxD1 || | + | | RxD1 || J2.1 || 14 || out |
|- | |- | ||
− | | TxD1 || | + | | TxD1 || J2.3 || 11 || in |
|- | |- | ||
− | | GPIO 168 || | + | | GPIO 168 || J2.5 || 8 || out |
|- | |- | ||
− | | GPIO 167 || | + | | GPIO 167 || J2.7 || 5 || in |
|- | |- | ||
<!-- slave 3, COM board, top --> | <!-- slave 3, COM board, top --> | ||
Line 97: | Line 97: | ||
<!-- slave 4, Sensor board, bottom --> | <!-- slave 4, Sensor board, bottom --> | ||
| rowspan=8 | slave 4:<br />[[HiRel/CanSat/Slave_Sensors|Sensors]] || rowspan=4 | bottom | | rowspan=8 | slave 4:<br />[[HiRel/CanSat/Slave_Sensors|Sensors]] || rowspan=4 | bottom | ||
− | | CS_n || | + | | CS_n || J2.2 || 15 || out |
|- | |- | ||
− | | MOSI || | + | | MOSI || J2.4 || 12 || out |
|- | |- | ||
− | | MISO || | + | | MISO || J2.6 || 9 || in |
|- | |- | ||
− | | SClk || | + | | SClk || J2.8 || 6 || out |
|- | |- | ||
<!-- slave 4, sensor board, top --> | <!-- slave 4, sensor board, top --> | ||
Line 109: | Line 109: | ||
| int_n || J3.2 || 23 || in | | int_n || J3.2 || 23 || in | ||
|- | |- | ||
− | | n.c. || J3.4 || 26 | + | | n.c. || J3.4 || 26 || |
|- | |- | ||
− | | n.c. || J3.6 || 30 | + | | n.c. || J3.6 || 30 || |
|- | |- | ||
| cnvt_n || J3.8 || 33 || out | | cnvt_n || J3.8 || 33 || out |
Revision as of 08:33, 29 May 2015
|
This board will be the master board on the HiRel/CanSat.
Type | CanSat Master FPGA | Schematic | UCF | Description |
---|---|---|---|---|
V1.0 | CanSat Master FPGA v1.0 Schematic PDF | CanSat Master FPGA v1.0 UCF Files | Spartan 6 XC6SLX9 and 8Mb M25P80 SPI PROM |
System
The design contains a soft-core processor controlling the different slaves of the CanSat via peripheral devices attached to it by an AHB-lite bus system.
Connections
The FPGA board hosts a 106.25 MHz oscillator and a button which can be used as a reset signal.
Signal | FPGA pin | FPGA dir |
---|---|---|
clock | 16 | in |
reset_n | 2 | in |
The FPGA board connectors consist of 4 dual Pmods, each having 12 pins. The Pmods are connected to the slave boards via the bottom and the top ring.
board | connector | Signal | Pmod pin | FPGA pin | FPGA dir |
---|---|---|---|---|---|
slave 1: Power |
bottom | TxD | J1.1 | 127 | in |
RxD | J1.3 | 124 | out | ||
LED 0 | J1.5 | 121 | out | ||
LED 1 | J1.7 | 118 | out | ||
top | switch 3 | J4.1 | 133 | in | |
switch 2 | J4.3 | 137 | in | ||
switch 1 | J4.5 | 139 | in | ||
switch 0 | J4.7 | 141 | in | ||
slave 2: Radio |
bottom | RxD | J1.2 | 126 | out |
TxD | J1.4 | 123 | in | ||
reset_n | J1.6 | 119 | out | ||
sleep request | J1.8 | 117 | out | ||
top | RSSI PWM | J4.2 | 134 | in | |
associate | J4.4 | 138 | in | ||
DIO | J4.6 | 140 | inout | ||
sleep_n | J4.8 | 142 | in | ||
slave 3: Computer On Module |
bottom | RxD1 | J2.1 | 14 | out |
TxD1 | J2.3 | 11 | in | ||
GPIO 168 | J2.5 | 8 | out | ||
GPIO 167 | J2.7 | 5 | in | ||
top | HSOLF | J3.2 | 24 | in | |
HSORF | J3.4 | 27 | in | ||
AUXRF | J3.6 | 32 | out | ||
AUXLF | J3.8 | 35 | out | ||
slave 4: Sensors |
bottom | CS_n | J2.2 | 15 | out |
MOSI | J2.4 | 12 | out | ||
MISO | J2.6 | 9 | in | ||
SClk | J2.8 | 6 | out | ||
top | int_n | J3.2 | 23 | in | |
n.c. | J3.4 | 26 | |||
n.c. | J3.6 | 30 | |||
cnvt_n | J3.8 | 33 | out |
Flash
The FPGA has an attached M25P80 SPI flash of 8 Mb.
FPGA comparisons
The choice of the FPGA was based on a comparison of synthesis results of a simple AHB-Lite system.
Manufacturer | Device | Estimated Frequency | LUTs / CoreCells | Memory | ||
---|---|---|---|---|---|---|
[MHz] | % | Needed | Available | |||
Xilinx | XC6SLX9 | 75.3 | 807 | 13 | 4 | 32 |
Microsemi | AGL60 | 16.4 | 56896 | 3704 | 2 | 4 |
Microsemi | AGL250 |
As it is visible in the table above, the smaller Microsemi Igloo devices are too small. Bigger Microsemi Igloo devices however are not easily available and also quite expensive (>80$). On the other hand the Xilinx Spartan 6 FPGAs are quite spacious, immediately available and have a reasonable price (<20$). Furthermore we already use them successfully on our FPGArack board.