Tools/Xilinx ISE/ISE Libraries
Compiling Simulation Libraries
To be able to simulate Xilinx IPs or netlists, one or more of the simulation libraries
might be needed. These libraries can be compiled with a tool provided with ISE.
These libraries can be linked as downstream only libraries with a ModelSim mapping in Mentor HDL-Designer or directly be mapped inside the simulator.
Running the tool
There are different ways to launch the tool:
- When you are using XPS as stand-alone (not launched from ISE), the tool can be launched in the menu Simulation => Compiling Simulation Libraries.
- On Windows the tool Simulation Library Compilation Wizard can be found in the Start Menu Start => Xilinx ISE Design Suite XX.X => ISE Design Tools => 64-bit Tools or in ISE select the FPGA in question in the Design Panel and select Design Utilities => Compile HDL Simulation Libraries in the Process Panel, in this case, only the libraries for the selected FPGA are compiled (see below).
- On Linux the command compxlib can be executed in the console.
Each chapter below corresponds to a window in the GUI.
Selecting a Simulator
On the first window a simulator has to be chosen. Verify that the Simulator Executable Location matches the simulator you like to use.
The second window serves to select the simulation language. VHDL is a good choice.
Select Device Families
Here the supported device families can be chosen. Be aware that choosing many families increases the needed hard-disk space as well as the compilation time significantly.
Select libraries for Functional and Timing Simulation
Choose the libraries regarding your needs. The selection may influence hard-disk space as well as the compilation time significantly.
For the further explanation the default path
ISE/<language>/<simulator>/<version>/<platform> is used.
During the compile process, a console like window is shown with information about the current actions. Please be patient. At the end a Compilation Summary is shown.
The same Compilation Summary as above is shown again in a more graphical way. If all went well the error count should be 0.
The libraries unisim, simprim and xilinxcorelib can be found at the location specified in the Output directory above:
The library secureip is only existing in Verilog in will be placed always under this language, independent of the HDL language chosen above: