Components/IP/Ethernet
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There are 2 [http://isi.hevs.ch/switzerland/robust-electronics.html ISI] [[Standards/Ethernet/IPs|Ethernet IP]] systems: | There are 2 [http://isi.hevs.ch/switzerland/robust-electronics.html ISI] [[Standards/Ethernet/IPs|Ethernet IP]] systems: | ||
| − | * the [[ | + | * the [[Components/Ethernet/IPs/UDP FIFO|light core]] with [[Standards/Ethernet/arp|ARP]] and UDP/IP capabilities |
| − | * the [[ | + | * the [[Components/Ethernet/IPs/dissolver|full core]] with additional [http://en.wikipedia.org/wiki/Internet_Control_Message_Protocol ICMP] (for ping) and [http://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol DHCP] support |
Both designs come in 3 blocks: | Both designs come in 3 blocks: | ||
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* a protocol decoder which retrieves the payload from the complete frame | * a protocol decoder which retrieves the payload from the complete frame | ||
* the application part where the user places one block for each function (protocol) to implement | * the application part where the user places one block for each function (protocol) to implement | ||
| + | |||
| + | == Testbench == | ||
| + | For both designs testbenches are given. They allow to send predefined packets to the Ethernet cores and record and save the packets sent by the Ethernet cores to a human readable text file. | ||
| + | The test benches are based on the [[Components/Ethernet/IPs/MII Testbench|MII receiver]] and the [[Components/Ethernet/IPs/MII Testbench|MII sender]]. | ||
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[[Category:Components]] [[Category:Designs]] [[Category:VHDL]] [[Category:IP]] | [[Category:Components]] [[Category:Designs]] [[Category:VHDL]] [[Category:IP]] | ||
Revision as of 08:58, 7 August 2013
These IPs can be found on the EDA Repository: svn: https://repos.hevs.ch/svn/eda/
There are 2 ISI Ethernet IP systems:
- the light core with ARP and UDP/IP capabilities
- the full core with additional ICMP (for ping) and DHCP support
Both designs come in 3 blocks:
- a MII to dual port RAM interface
- a protocol decoder which retrieves the payload from the complete frame
- the application part where the user places one block for each function (protocol) to implement
Testbench
For both designs testbenches are given. They allow to send predefined packets to the Ethernet cores and record and save the packets sent by the Ethernet cores to a human readable text file. The test benches are based on the MII receiver and the MII sender.
