Components/IP/VME
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* [[Hardware/FPGARackBackplane|HES-SO FPGA Rack Backplane]] | * [[Hardware/FPGARackBackplane|HES-SO FPGA Rack Backplane]] | ||
| − | = Bus | + | = Bus Specification = |
| + | * [[Standards/HEVs_%27VME%27_Backplane_Bus#Bus_Specifications|Bus Specifications]] | ||
| + | * [[Standards/HEVs_%27VME%27_Backplane_Bus#Signal_Mapping|Signal Mapping]] | ||
| + | * [[Standards/HEVs_%27VME%27_Backplane_Bus#Timing_diagrams|Timing Diagrams]] | ||
Revision as of 15:11, 23 January 2014
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The HES-SO VME IP Core was designed within the project BasMI. Is is used in the VME Backplanes for interconnecting different Rack Boards together
Introduction
At the moment of the creation of this document, some new FPGA development cards have been realized at the HES-SO Valais/Wallis Sion. There are the [[FPGA Rack V1 board (successor of the old FPGA-EBS, for general purpose) and the * FPGARack AD/DA V1 board (initially done for the OLGM project).
These new PCBs have Eurocard (100x160mm) size and a DIN41612 3x32pin connector soldered. So, this document describes the work realized around this new communication bus (physical and VHDL). The goal was to define and create the communication in the aforementioned DIN41612 conncetor. It was choosen to create a modified VME Bus called HVME (HES-SO VME).
