Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit
This is the knowledge database of the HES-SO Valais Wallis Institute of Systems Engineering
Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.
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- Supported Families: SmartFusion2, SmartFusion, Fusion, ProASIC3, ProASIC3E, ProASIC3L, IGLOO, IGLOOe, IGLOO+
- Multiple performance improvements
- New compact library format; Wave Window improvements
- VHDL 2008 support improvements; Inclusion of VHDL-2008 OSVVM libraries
- Questa only: New UVM, VM features; enhanced Power Aware Simulation
- New Supported/ Enhanced VHDL 2008 Constructs
- Task / Flow Updates
- Block Diagram and IBD Enhancements
- IP updates
- further Device Support for Virtex-7, Zynq-7000 and Defenense-Grade Kintex-7Q, Virtex-7Q
This update brings following new features to the 10.0 release:
- Improved GUI performance – Improved structure window and objects window
- VHDL Improvements - Support for significant portions of VHDL 2008 and Preservation
of user case in identifiers
- New advanced debug features including schematic view debug and automatic causality
- Improved WLF debugging and new Code Coverage Analysis Pane
- Improved Altera and Xilinx Vivado support
- New Microsemi SmartFusion2 Device
- Expanded SystemVerilog Support
- Improved Physical Plus for Xilinx devices
The IEEE Std 1800-2012 a.k.a. SystemVerilog is available for download
The 31 new features, 60 clarifications and 71 corrections of the standard include:
- Multiple inheritance !
- Soft constraints
- Uniqueness constraints
- A different global clock can be defined for each hierarchy scope
More infos here
The presentation slides can be downloaded here.
After 7 years of development, Qt 5.0, centered around Qt Quick with the full capabilities of OpenGL/OpenGL ES, has been released.
- Faster GUI with QML and QtQuick with special focus on low cost HW environments (mobile, embedded).
- Built-in OpenGL (ES) support
- Webkit and HTML5
- 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
- 166 MHz ARM® Cortex™-M3 microprocessor with 8Kbyte Instruction Cache
- connects to USB 2.0 HS OTG, CAN, SPI, I2C and Gigabit Ethernet
- static power 10mW during operation on the 50K LUT device
- 0 - 16 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
- Hard 800 mbps DDR2/3 controllers with SECDED (aka ECC or EDAC) protection
- but no more DAC/ADC
- samples available now, first production silicon slated for early 2013
This bugfix release is available for download now.