Revision as of 14:50, 18 May 2015 by Francois.corthay
In order to divide the clock frequency, a Digital Clock manager (DCM) module can be instantiated.
In a Spartan-6 FPGA, the associated module is a
DCM_SP or a
Here a sample code:
library UNISIM; use UNISIM.vcomponents.all; I_DCM: dcm_clkgen generic map ( clkfx_multiply => 3, clkfx_divide => 8, clkin_period => 10.0 ) port map ( rst => '0', freezedcm => '0', clkin => clockIn, clkfx => clock );
Adding the UniSim to the HDS tool can be done with:
unisim = $ISE_HOME/ISE/vhdl/src/unisims