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* [[Eln/labs/presentations/COM|Lab COM]] | * [[Eln/labs/presentations/COM|Lab COM]] | ||
− | = | + | = To do = |
+ | |||
+ | == corrections for the lab instructions == | ||
lab NUM : # bits of constants in first drawing | lab NUM : # bits of constants in first drawing | ||
Line 32: | Line 34: | ||
Testbenches: <code>sequence</code> is now a reserved word. | Testbenches: <code>sequence</code> is now a reserved word. | ||
Use the label <code>testSequence</code> instead. | Use the label <code>testSequence</code> instead. | ||
+ | |||
+ | Ex FSM 5.6 : cof solution doesn't beep correctly? | ||
+ | |||
+ | Ex FSM 6.6 : Q1 last riging edge should be just after rising edge of clock | ||
+ | |||
+ | Ex FSM 4.3 : state 01 wrong Y Siganl | ||
+ | |||
+ | == Libraries == | ||
+ | |||
+ | Add verctored inverter to library gates | ||
= Course support = | = Course support = | ||
Line 37: | Line 49: | ||
== Demonstration circuit == | == Demonstration circuit == | ||
− | At the beginning of the semester a hardware demonstration is shown to the students so that they get a notion of what we are talking about. | + | At the beginning of the semester a [[Support/hardware_demonstration|hardware demonstration]] |
+ | is shown to the students so that they get a notion of what we are talking about. | ||
− | It is a circuit which plays a little music or a single note from an FPGA on a loudspeaker. In parallel the output signals are visualized on an oscilloscope. | + | It is a circuit which plays a little music or a single note from an FPGA on a loudspeaker. |
+ | In parallel the output signals are visualized on an oscilloscope. | ||
The number of bits used to generate the notes can be modified. | The number of bits used to generate the notes can be modified. | ||
− | This allows to show what | + | This allows to show what a digital signal is, |
+ | show and hear the meaning of bits and vectors as well as frequency. | ||
− | The FPGA design can be found at: https:// | + | The FPGA design can be found at: https://gitlab.hevs.ch/course/ElN/eln-support. |
= Tools setup = | = Tools setup = | ||
Line 53: | Line 68: | ||
Additionally to launching the circuit design application, the script sets the following environment variables: | Additionally to launching the circuit design application, the script sets the following environment variables: | ||
* <code>DESIGN_NAME</code> : the name of the design, it is used for: | * <code>DESIGN_NAME</code> : the name of the design, it is used for: | ||
− | |||
− | |||
** the concatenated VHDL file name | ** the concatenated VHDL file name | ||
− | ** the <code>.ucf</code> user constraints file | + | ** the <code>.ucf</code> or <code>.pdc</code> user constraints file names |
− | * <code>HDS_LIBS</code> : the file defining the mappings of the libraries to the filesystem | + | ** the <code>.xise</code> or <code>.prj</code> project file names |
+ | * <code>HEI_LIBS_DIR</code> : the file defining location of the libraries, by default they are in the project folder under <code>Libs</code> | ||
+ | * <code>HDS_LIBS</code> : the file defining the mappings of the libraries to the filesystem, the file is called <code>hds.hdp</code> | ||
* <code>SIMULATION_DIR</code> : a directory where <code>.do</code> and other files are found for the simulation (and the synthesis) | * <code>SIMULATION_DIR</code> : a directory where <code>.do</code> and other files are found for the simulation (and the synthesis) | ||
+ | |||
* <code>HDS_USER_HOME</code> : the directory with the HDL designer settings; it is different for Linux and Windows users | * <code>HDS_USER_HOME</code> : the directory with the HDL designer settings; it is different for Linux and Windows users | ||
* <code>HDS_TEAM_HOME</code> : a further directory with HDL designer settings | * <code>HDS_TEAM_HOME</code> : a further directory with HDL designer settings | ||
+ | * <code>SCRATCH_DIR</code> : the directroy containing the intermediate files for modelsim simulations. Can be erased at any time | ||
* <code>CONCAT_DIR</code> : the directory containing the single-file VHDL and the user constraints file | * <code>CONCAT_DIR</code> : the directory containing the single-file VHDL and the user constraints file | ||
− | * <code> | + | |
− | * <code> | + | * <code>HDS_HOME</code> : the directory containing the HDL Designer executable |
− | * <code> | + | * <code>MODELSIM_HOME</code> : the directory containing the Modelsim simulator executable |
− | * <code>HDS_PROJECT_DIR</code> is set automatically by HDL Designer | + | |
+ | If synthesis is used, the scrips also set: | ||
+ | * <code>SYNTHESIS_HOME</code> : the directory containing the synthesis Project executables | ||
+ | * <code>SYNTHESIS_BASE_DIR</code> : the directory containing the Xilinx <code>.xise</code> or the the Libero <code>.prj</code> project file | ||
+ | * <code>SYNTHESIS_WORK_DIR</code> : the directory containing intermediate synthesis project files. Created anew after each program start by the scripts in the scratch directory | ||
+ | |||
+ | The environment varaible <code>HDS_PROJECT_DIR</code> is set automatically by HDL Designer. | ||
== Hardware implementation == | == Hardware implementation == | ||
Line 78: | Line 101: | ||
The file generation step ends with the script <code>trimLibs.pl</code> | The file generation step ends with the script <code>trimLibs.pl</code> | ||
− | which transforms <code> | + | which transforms <code><i>concat_file</i>.vhd</code> into <code><i>designName</i>.vhd</code> |
− | The script launching the EDA tool defines the environment variable <code> | + | The script requires two arguments: |
− | which specifies the directory where the | + | * <code>ARGV[0]</code> - input file spec containing references to regular libraries |
+ | * <code>ARGV[1]</code> - output file spec with the library references changed to the <code>work</code> library | ||
+ | |||
+ | The HDL Designer tasks require to have a HDL Designer user variable called <code>concat_file</code> with value <code>concatenated</code> | ||
+ | |||
+ | === Xilinx ISE synthesis === | ||
+ | |||
+ | The synthesis is performed in a scratch directory due to the volume of the files generated by the tool. | ||
+ | |||
+ | The synthesis step ends with the script <code>update_ise.pl</code> | ||
+ | which updates the <code>.vhd</code> and <code>.ucf</code> file names in the <code>.xise</code> configuration file. | ||
+ | |||
+ | The script launching the EDA tool defines the environment variable <code>ISE_WORK_DIR</code> | ||
+ | which specifies the directory where the synthesis takes place. | ||
This step requires the user variables: | This step requires the user variables: | ||
− | * <code>%( | + | * <code>%(task_ISEBinPath)</code> which is set to <code>$ISE_HOME</code> |
+ | * <code>%(task_ISEPath)</code> which is set to <code>$ISE_WORK_DIR</code> | ||
* <code>%(designName)</code> which is set to <code>$DESIGN_NAME</code> | * <code>%(designName)</code> which is set to <code>$DESIGN_NAME</code> | ||
− | === | + | and the environment variable: |
+ | * <code>$CONCAT_DIR</code> | ||
+ | |||
+ | === Microsemi Libero synthesis === | ||
The synthesis is performed in a scratch directory due to the volume of the files generated by the tool. | The synthesis is performed in a scratch directory due to the volume of the files generated by the tool. |
Latest revision as of 15:00, 21 December 2020
|
Lab presentations
The original files for the labs is found on the HEVs GitLab.
A little information allows to drive the students into the labs:
To do
corrections for the lab instructions
lab NUM : # bits of constants in first drawing
Ex NUM f : 4.2 soustracions -> soustractions
lab ADD: add an assert at the end of the testbench to verify that all tests have been passed only by looking at the transcript
lab MUL: add testbench multiplying sin(wt) with sin(2wt) and analyse the required number of bits of the result (2n for unsigned, 2n-1 for signed)
Lab ALU: change the SR / SHL operation to enable shifting don't cares
How to write a report -> Moodle
Testbenches: sequence
is now a reserved word.
Use the label testSequence
instead.
Ex FSM 5.6 : cof solution doesn't beep correctly?
Ex FSM 6.6 : Q1 last riging edge should be just after rising edge of clock
Ex FSM 4.3 : state 01 wrong Y Siganl
Libraries
Add verctored inverter to library gates
Course support
Demonstration circuit
At the beginning of the semester a hardware demonstration is shown to the students so that they get a notion of what we are talking about.
It is a circuit which plays a little music or a single note from an FPGA on a loudspeaker. In parallel the output signals are visualized on an oscilloscope. The number of bits used to generate the notes can be modified.
This allows to show what a digital signal is, show and hear the meaning of bits and vectors as well as frequency.
The FPGA design can be found at: https://gitlab.hevs.ch/course/ElN/eln-support.
Tools setup
Launching the tools
The EDA tools are launched by a script. Additionally to launching the circuit design application, the script sets the following environment variables:
-
DESIGN_NAME
: the name of the design, it is used for:- the concatenated VHDL file name
- the
.ucf
or.pdc
user constraints file names - the
.xise
or.prj
project file names
-
HEI_LIBS_DIR
: the file defining location of the libraries, by default they are in the project folder underLibs
-
HDS_LIBS
: the file defining the mappings of the libraries to the filesystem, the file is calledhds.hdp
-
SIMULATION_DIR
: a directory where.do
and other files are found for the simulation (and the synthesis)
-
HDS_USER_HOME
: the directory with the HDL designer settings; it is different for Linux and Windows users -
HDS_TEAM_HOME
: a further directory with HDL designer settings -
SCRATCH_DIR
: the directroy containing the intermediate files for modelsim simulations. Can be erased at any time -
CONCAT_DIR
: the directory containing the single-file VHDL and the user constraints file
-
HDS_HOME
: the directory containing the HDL Designer executable -
MODELSIM_HOME
: the directory containing the Modelsim simulator executable
If synthesis is used, the scrips also set:
-
SYNTHESIS_HOME
: the directory containing the synthesis Project executables -
SYNTHESIS_BASE_DIR
: the directory containing the Xilinx.xise
or the the Libero.prj
project file -
SYNTHESIS_WORK_DIR
: the directory containing intermediate synthesis project files. Created anew after each program start by the scripts in the scratch directory
The environment varaible HDS_PROJECT_DIR
is set automatically by HDL Designer.
Hardware implementation
The hardware implementation starts form the board
library.
Concatenation
A first tool generates a single file which contains the whole design.
With this, the libraries are flattened and all the components are considered to reside in the library work
.
This could be of trouble if two libraries were to contain a component with the same name.
The file generation step ends with the script trimLibs.pl
which transforms concat_file.vhd
into designName.vhd
The script requires two arguments:
-
ARGV[0]
- input file spec containing references to regular libraries -
ARGV[1]
- output file spec with the library references changed to thework
library
The HDL Designer tasks require to have a HDL Designer user variable called concat_file
with value concatenated
Xilinx ISE synthesis
The synthesis is performed in a scratch directory due to the volume of the files generated by the tool.
The synthesis step ends with the script update_ise.pl
which updates the .vhd
and .ucf
file names in the .xise
configuration file.
The script launching the EDA tool defines the environment variable ISE_WORK_DIR
which specifies the directory where the synthesis takes place.
This step requires the user variables:
-
%(task_ISEBinPath)
which is set to$ISE_HOME
-
%(task_ISEPath)
which is set to$ISE_WORK_DIR
-
%(designName)
which is set to$DESIGN_NAME
and the environment variable:
-
$CONCAT_DIR
Microsemi Libero synthesis
The synthesis is performed in a scratch directory due to the volume of the files generated by the tool.
The synthesis step ends with the script update_ise.pl
which updates the .vhd
and .ucf
file names in the .xise
configuration file.
The script launching the EDA tool defines the environment variable ISE_WORK_DIR
which specifies the directory where the synthesis takes place.
This step requires the user variables:
-
%(task_ISEBinPath)
which is set to$ISE_HOME
-
%(task_ISEPath)
which is set to$ISE_WORK_DIR
-
%(designName)
which is set to$DESIGN_NAME
and the environment variable:
-
$CONCAT_DIR
HDL Student version
Student directories
The source files should be placed in U:\SEm_labs
or any other path without spaces or Umlaut/accents.
Temporary files are placed in C:\Temp\EDA\<userName>\<designName>
.
Master data
The sources of the documentation for this course are stored at I:\Bachelor\SI\Cours\2131_Ele\ELN
. You need to be enrolled in this course to see this folder.
All the source code is hosted on https://repos.hevs.ch/svn/eda/VHDL/labs/:
https://repos.hevs.ch/svn/eda/VHDL/labs/ELN_labs/,
https://repos.hevs.ch/svn/eda/VHDL/labs/ELN_cursor,
https://repos.hevs.ch/svn/eda/VHDL/labs/ELN_chrono/
Student data
The students project is a subset of the master data, with some blocks and architectures removed.
Upload to R for studens
The script:
- locally
- deletes all intermediate files in the project
- on
R
- deletes the folder
R:\SYND\Ele_2131\ELN\Labs\ELN_labs
- deletes the folder
R:\ETE\ElN_8215\Labs\ELN_labs
- copies the local project to the above mentioned folders
- removes the files and folders not intended for students' eyes
- modifies the default view to studentVersion
- deletes for defined blocks all architectures except studentVersion
- creates a compressed file
- deletes the folder