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| − | {{private}}
| + | #REDIRECT [[Kart]] |
| − | {{TOC right}}
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| − | == FPGA boards ==
| + | [[Category:Kart]] |
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| − | The FPGA modules use MicroSemi [http://www.actel.com/products/igloo/ IGLOO] low-power FPGAs.
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| − | The boards have been designed for AGL125 in a VQ100 package.
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| − | However, it is possible to mount the following devices with the same package on that board:
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| − | * AGL060: 1'536 VersaTiles, 4 4'608-bit RAMs
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| − | * AGL125: 3'072 VersaTiles, 8 4'608-bit RAMs
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| − | * AGL250: 6'144 VersaTiles, 8 4'608-bit RAMs
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| − | One VersaTile can implement a 3-input combinatorial function or an E-flipflop.
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| − | === Pin Compatibility ===
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| − | As a simple compatibility rule for these devices, one should use:
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| − | * pins 43, 60, 93 and 94 for I/Os but not as a clock inputs
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| − | * pin 99 tied to GNDQ
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| − | * pin 100 tied to VMV0 (3.3 V)
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| − | === Global Clock Networks ===
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| − | Note that pin names starting with '''GF''' and '''GC''' are associated with the chip global networks, and GA, GB, GD, and GE are used for quadrant global networks.
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| − | In case of the AGL060 - AGL250 the following pins are truly Global Clocks.
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| − | * pins 10, 11, 13, 15, 16 for Network GF
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| − | * pins 61, 62, 63, 64, 65 for Network GC
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| − | == Synthesis results ==
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| − | The device usage gives an idea if the synthesis has worked properly.
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| − | Here the results for the AGLN125V5:
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| − | * [[Kart/DC motor controller#FPGA design|DC motor]]: 13 %
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| − | * [[Kart/stepper motor controller#FPGA design|stepper motor]]: 25 %
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| − | * I/O board: 34 %
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