Components/Libraries/VHDL/SPI
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(Created page with "{{TOC right}} The toplevel block <code>spiFIFO</code> provides a SPI interface and two FIFO interface. The Slave FIFO interface makes the received data on during a write Tran...")
(Created page with "{{TOC right}} The toplevel block <code>spiFIFO</code> provides a SPI interface and two FIFO interface. The Slave FIFO interface makes the received data on during a write Tran...")
Latest revision as of 14:43, 1 October 2012
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The toplevel block spiFIFO provides a SPI interface and two FIFO interface.
The Slave FIFO interface makes the received data on during a write Transfer accessible.
The Master FIFO interface serves as buffer for data to send on the SPI line.
Blocks
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spiFIFO - Toplevel bloc
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spiTransceiver - Low Level SPI bloc
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spiTimer - Generates en signal for sending frame and SPI_clk
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spiWrite - sends data written on the FIFO interface to the Transceiver
Depends on
Is used by
- <none>
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