Languages
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* [[VHDL_syntax|VHDL Syntax]] | * [[VHDL_syntax|VHDL Syntax]] | ||
* [[VHDL_libraries|VHDL Libraries]] | * [[VHDL_libraries|VHDL Libraries]] | ||
− | * [[VHDL_examples|VHDL | + | * [[VHDL_examples|VHDL Examples]] |
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* [[SystemVerilog_syntax|System Verilog Syntax]] | * [[SystemVerilog_syntax|System Verilog Syntax]] | ||
* [[OpenMethodMethodology|Open Method Methodology]] | * [[OpenMethodMethodology|Open Method Methodology]] | ||
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+ | [[Category:Languages]] |
Revision as of 15:12, 7 February 2012
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VHDL
Tcl_Tk