Hardware/Parallelport/heb lcd
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− | = | + | = LCD, buttons and LED boards = |
− | + | The HEB LCD board contains 4 Buttons and 8 LEDs. | |
− | The HEB LCD board contains 4 Buttons and 8 LEDs. | + | The LCD part is not functional on the V1.0 boards. |
{|class=wikitable | {|class=wikitable | ||
|- | |- | ||
− | ! Version || Photo || Schematics || Description | + | ! Version || Photo || Schematics || Stock || Description |
|- | |- | ||
− | | V1.0 || [[File:FPGA_PP_HEB_lcd.jpg|200px|HEB LCD]] || [[Media:FPGA_PP_HEB_lcd_schematic.pdf|FPGA HEB Matrix Schematic PDF]] || Parallelboard extention with 4 Buttons, 8 Leds and an optional LCD | + | | V2.0 || [[File:FPGA_PP_HEB_lcd_v2.png|200px|HEB LCD]] <br>[[Hardware/Stock_PP#HEB LCD|boards 10-18]] || [[Media:FPGA_PP_HEB_lcd_v2_schematic.pdf|FPGA HEB LCD Schematic PDF]] || [[Hardware/Stock_PP#HEB_LCD_V2.0|9 fully mounted]] || Parallelboard extention with 4 Buttons, 8 Leds and an 4 Row LCD |
+ | |- | ||
+ | | V1.0 || [[File:FPGA_PP_HEB_lcd.jpg|200px|HEB LCD]] || [[Media:FPGA_PP_HEB_lcd_schematic.pdf|FPGA HEB Matrix Schematic PDF]] || [[Hardware/Stock_PP#HEB_LCD_V1.0|9 fully mounted]] || Parallelboard extention with 4 Buttons, 8 Leds and an optional LCD, however the LCD never worked and therefore no card with LCD exists. | ||
|} | |} | ||
− | [[Category:Hardware]] [[Category:Parallelport]] | + | = Connectors = |
+ | |||
+ | Version 1 and version 2 HEB-LCD boards are '''NOT''' pin compatible. | ||
+ | |||
+ | {| class="wikitable" style="margin: 20pt; text-align:center" | ||
+ | ! conn.<br />pin || V2<br />signal || V1<br />signal || FPGA-EBS<br />pin || scope="col" style="width: 30px; background-color:white" | ||conn.<br />pin || V2<br />signal || V1<br />signal || FPGA-EBS<br />pin | ||
+ | |- | ||
+ | | 1 || LCD CS_n || LED 8 || A11 || style="background-color:white" | || 2 || LCD RST_n || || A13 | ||
+ | |- | ||
+ | | 3 || LCD A0 || LED 7 || A14 || style="background-color:white" | || 4 || LCD SCL || || D7 | ||
+ | |- | ||
+ | | 5 || LCD SI || LED 6 || C7 || style="background-color:white" | || 6 || LED 1 || || E9 | ||
+ | |- | ||
+ | | 7 || LED 2 || LED 5 || A8 || style="background-color:white" | || 8 || LED 3 || || F11 | ||
+ | |- | ||
+ | | 9 || LED 4 || LED 4 || B11 || style="background-color:white" | || GND || rowspan=9 colspan=3| power<br />supply | ||
+ | |- | ||
+ | | 11 || LED 5 || LED 3 || B13 || style="background-color:white" | || GND | ||
+ | |- | ||
+ | | 13 || LED 6 || LED 2 || B14 || style="background-color:white" | || GND | ||
+ | |- | ||
+ | | 15 || LED 7 || LED 1 || E7 || style="background-color:white" | || GND | ||
+ | |- | ||
+ | | 17 || LED 8 || button 4 || E8 || style="background-color:white" | || GND | ||
+ | |- | ||
+ | | 19 || button 1 || button 3 || G9 || style="background-color:white" | || GND | ||
+ | |- | ||
+ | | 21 || button 2 || button 2 || F9 || style="background-color:white" | || GND | ||
+ | |- | ||
+ | | 23 || button 3 || button 1 || F7 || style="background-color:white" | || GND | ||
+ | |- | ||
+ | | 25 || button 4 || || F8 || style="background-color:white" | || 3.3 V | ||
+ | |} | ||
+ | |||
+ | = IP core = | ||
+ | |||
+ | The [[Components/IP/HEB_LCD|LCD IP core]] allows to write text on the LCD. | ||
+ | The core initializes the LCD and draws up to 22 per line based on a pattern defined in a ROM. | ||
+ | |||
+ | [[Category:Hardware]] [[Category:Parallelport]] [[Category:HEB]] |
Latest revision as of 16:38, 18 December 2015
|
LCD, buttons and LED boards
The HEB LCD board contains 4 Buttons and 8 LEDs. The LCD part is not functional on the V1.0 boards.
Version | Photo | Schematics | Stock | Description |
---|---|---|---|---|
V2.0 | ![]() boards 10-18 |
FPGA HEB LCD Schematic PDF | 9 fully mounted | Parallelboard extention with 4 Buttons, 8 Leds and an 4 Row LCD |
V1.0 | ![]() |
FPGA HEB Matrix Schematic PDF | 9 fully mounted | Parallelboard extention with 4 Buttons, 8 Leds and an optional LCD, however the LCD never worked and therefore no card with LCD exists. |
Connectors
Version 1 and version 2 HEB-LCD boards are NOT pin compatible.
conn. pin |
V2 signal |
V1 signal |
FPGA-EBS pin |
conn. pin |
V2 signal |
V1 signal |
FPGA-EBS pin | |
---|---|---|---|---|---|---|---|---|
1 | LCD CS_n | LED 8 | A11 | 2 | LCD RST_n | A13 | ||
3 | LCD A0 | LED 7 | A14 | 4 | LCD SCL | D7 | ||
5 | LCD SI | LED 6 | C7 | 6 | LED 1 | E9 | ||
7 | LED 2 | LED 5 | A8 | 8 | LED 3 | F11 | ||
9 | LED 4 | LED 4 | B11 | GND | power supply | |||
11 | LED 5 | LED 3 | B13 | GND | ||||
13 | LED 6 | LED 2 | B14 | GND | ||||
15 | LED 7 | LED 1 | E7 | GND | ||||
17 | LED 8 | button 4 | E8 | GND | ||||
19 | button 1 | button 3 | G9 | GND | ||||
21 | button 2 | button 2 | F9 | GND | ||||
23 | button 3 | button 1 | F7 | GND | ||||
25 | button 4 | F8 | 3.3 V |
IP core
The LCD IP core allows to write text on the LCD. The core initializes the LCD and draws up to 22 per line based on a pattern defined in a ROM.