Components/Designs/VHDL template
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* https://repos.hevs.ch/viewvc/eda | * https://repos.hevs.ch/viewvc/eda | ||
− | = | + | = Tools = |
− | The | + | The recommended version of the tools to use are marked with '''''EDA libs''''' in [[Tools/Versions]]. |
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= Directory Structure = | = Directory Structure = |
Latest revision as of 09:12, 10 June 2016
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There is a template VHDL Design available where most used IP Cores developed by HES-SO Valais are included. If you need to start a new project and you need a VHDL Design to start with, this is the place.
The following pages explains how this design is build and can be reused for a different project.
SVN Repository
You can find the Template VHDL Design in our SVN Repository.
For viewing the Repository in a browser use the following address
Tools
The recommended version of the tools to use are marked with EDA libs in Tools/Versions.
Directory Structure
└───VHDL -- Design main folder ├───eln_board -- Project folder for ELN_board testing │ ├───Board -- Board Toplevel design (with Synchronisation) │ │ ├───concat -- Generated concat VHDL & UCF file │ │ ├───hdl │ │ ├───hds │ │ └───ise -- ISE Project file │ ├───BoardTester -- Board Toplevel design (without Synchronisation) │ │ ├───hdl │ │ └───hds │ ├───BoardTester_test -- Testbench for BoardTester │ │ ├───hdl │ │ └───hds │ ├───Prefs -- HDL Designer Prefs for Project ELN_Board │ │ ├───dc_user │ │ ├───dp_user │ │ ├───hds_team │ │ ├───hds_user │ │ └───hds_user-linux │ └───Simulation -- Folder for Sim File e.g. *.do, *.eth, *.txt, *.srec ├───fgpa_rack -- Project folder for FPGA_Rack testing │ ├───Board -- Board Toplevel design (with Synchronisation) │ │ ├───concat -- Generated concat VHDL & UCF file │ │ ├───hdl │ │ ├───hds │ │ └───ise -- ISE Project file │ ├───BoardTester -- Board Toplevel design (without Synchronisation) │ │ ├───hdl │ │ └───hds │ ├───BoardTester_test -- Testbench for BoardTester │ │ ├───hdl │ │ └───hds │ ├───Prefs -- HDL Designer Prefs for Project FPGA_Rack │ │ ├───dc_user │ │ ├───dp_user │ │ ├───hds_team │ │ ├───hds_user │ │ └───hds_user-linux │ └───Simulation -- Folder for Sim File e.g. *.do, *.eth, *.txt, *.srec └───libs -- Folder for all NON-Project specific libraries ├───CommandLine -- Library Commandline for Commandline parsing │ ├───hdl │ └───hds ├───CommandLine_test -- Testbench for Library Commandline │ ├───hdl │ └───hds ├───Common -- Library Common with useful packages │ ├───hdl │ └───hds ├───Common_test -- Testbench for Library Common │ ├───hdl │ └───hds ├───Cordic -- Library Cordic for Sinus / Cosinus generator │ ├───hdl │ └───hds ├───Cordic_test -- Testbench for Library Cordic │ ├───hdl │ └───hds ├───Ethernet -- Library Ethernet for 100Mbps Transceiver │ ├───hdl │ └───hds ├───Ethernet_test -- Testbench for Library Ethernet │ ├───hdl │ └───hds ├───I2C -- Library I2C for I2C commmunication │ ├───hdl │ └───hds ├───I2C_test -- Testbench for Library I2C │ ├───hdl │ └───hds ├───Led -- Library Led for HEB-LCD communication │ ├───hdl │ └───hds ├───Led_test -- Testbench for Library Led │ ├───hdl │ └───hds ├───Memory -- Library Memory for BRAM, FIFO, SDRAM Controller, Flash Controller │ ├───hdl │ └───hds ├───Memory_test -- Testbench for Library Memory │ ├───hdl │ └───hds ├───RS232 -- Library RS232 for RS232 Communication │ ├───hdl │ └───hds ├───RS232_test -- Testbench for Library RS232 │ ├───hdl │ └───hds ├───SPI -- Library SPI for SPI Communication │ ├───hdl │ └───hds └───SPI_test -- Testbench for Library SPI ├───hdl └───hds
Project Files
There are multiple level of "Project Files".
hdldesigner.bat
This file is specific to each project and can be found in the Project folder e.g. VHDL/eln_board/hdlDesigner.bat
It does the following:
- Define environment variables used
- by HDL-Designer
- by the project
- Prepare SCRATCH_DIR for intermediate files
- Create SCRATCH_DIR
- Copy ISE Designfiles into it
- Launch HDL-Designer
hds.hdp
This file is specific to each project and can be found in the Prefs folder inside the Project folder e.g. VHDL/eln_board/Prefs/hds.hdp
It contains:
- Location of all HDL-Designer libraries
This file has multiple sections
Section | Description |
---|---|
[Concat] |
Defines location of the Concatenation folder. Only needed for the Board library
|
[Modelsim] |
Defines location of the Modelsim work folder.
|
[hdl] |
Defines location of the hdl folder. For storing all pure *.vhd files
|
[hds] |
Defines location of the hds folder. For storing all HDL-Designer Design files such as Statemachines, Designblocs and other Graphical files.
|
[hds_settings] |
Defines the Design roots marker of libraries. |
[library_type] |
Defines library types (regular, standard) |
[shared] |
Defines Shared libraries |
Dependencies
This is a file located in the libs folder inside the VHDL folder. It shows all the dependencies of the libraries.
There is a certain syntax in this file, if you need to change it. Syntax
# This is a comment Libraryname: Lib_dependency1, Lib_dependency2 # Library with dependencies Libraryname: <none> # Library with no dependencies
Example
Common: <none> CommandLine: Common, RS232, I2C
In the future a tools could read these files and download only the necessary libraries for your project.
Using the Project
As "it is"
- Checkout SVN Repository
- Check project folder (eln_board, fpga_rack) and modify hdlDesigner.bat start script.
VHDL/eln_board/hdlDesigner.bat
- DONE
As Template
- Checkout SVN Repository
- Generate you own project folder under VHDL/
VHDL/projectname
- Copy needed filed and folder from example project (eln_board or fpga_rack)
Copy eln_board content to your project folder └───eln_board -- Project folder for ELN_board testing ├───Board -- Board Toplevel design (with Synchronisation) │ ├───concat -- Generated concat VHDL & UCF file │ ├───hdl │ ├───hds │ └───ise -- ISE Project file ├───BoardTester -- Board Toplevel design (without Synchronisation) │ ├───hdl │ └───hds ├───BoardTester_test -- Testbench for BoardTester │ ├───hdl │ └───hds ├───Prefs -- HDL Designer Prefs for Project │ ├───dc_user │ ├───dp_user │ ├───hds_team │ ├───hds_user │ └───hds_user-linux └───Simulation -- Folder for Sim File e.g. *.do, *.eth, *.txt, *.srec
- Modify hdlDesigner.bat in your projectfolder.
- Rename projectfolder/ise/*.xise into your $DESIGN_NAME defined in hdlDesigner.bat
- Rename projectfolder/concat/*.ucf into your $DESIGN_NAME defined in hdlDesigner.bat
- Modify UCF to your design
- Start HDLDesigner
- Delete and Create your own Design in BoardTester Library
- Delete and Create your own Toplevel Design in Board Library
- Delete and Create your own Testbench in BoardTester_test
- Delete and add you own Simulation files if needed, store you waveform files also here
- DONE