Hardware/CubeSat Gumstix/camera connector
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(→OV7670) |
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| 24 || CC4 / PowerDn || D14 | | 24 || CC4 / PowerDn || D14 | ||
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+ | |||
+ | = Camera modules = | ||
+ | |||
+ | The connector is meant for use with different camera modules. | ||
+ | |||
+ | == OV7670 == | ||
+ | |||
+ | The [http://www.arducam.com/camera-modules/0-3mp-ov7670/ OV7670] camera module has: | ||
+ | * selectable resolutions comprising [https://en.wikipedia.org/wiki/Video_Graphics_Array VGA], [https://en.wikipedia.org/wiki/Common_Intermediate_Format CIF] and their subsizes | ||
+ | * 16 bit [https://en.wikipedia.org/wiki/RGB_color_model RGB], [https://en.wikipedia.org/wiki/YUV YUV] or Bayer [https://en.wikipedia.org/wiki/Raw_image_format raw] data | ||
+ | * an [https://en.wikipedia.org/wiki/I²C I2C] control interface | ||
+ | |||
+ | [[File:Camera OV7670.jpg|center|500px]] | ||
+ | |||
+ | === Timing generation === | ||
+ | |||
+ | The camera module receives a master clock signal: <code>XCLK</code>. | ||
+ | This clock signal can be multiplied by 1, 4, 6 or 8 by a PLL (DBLV[7:6] at 6B<sub>h</sub>). | ||
+ | The resulting frequency can be divided by an even number ( 2*(CLKRC[5:0]+1), set at 11<sub>h</sub> ). | ||
+ | This provides the reference clock for the image acquisition. | ||
+ | |||
+ | The acquired image can be downsampled by a factor of 2, 4 or 8 (SCALING_PCLK_DIV[3:0] at 73<sub>h</sub>). | ||
+ | After this, a digital zoom out can be applied with a factor of 1 to 2 separately in the horizontal (REG74[6:0] at 74<sub>h</sub>) and vertical (REG75[6:0] at 75<sub>h</sub>) directions. | ||
+ | These operations can be enabled or disabled (COM3[3:2] at 0C<sub>h</sub>). | ||
+ | |||
+ | From these, the video control signals are generated: | ||
+ | * <code>VSYNC</code>: vertical sync. with programmable polarity | ||
+ | * <code>HREF</code>: enable signal for reading, with programmable polarity | ||
+ | * <code>PCLK</code>: pixel clock | ||
+ | |||
+ | === Configuration === | ||
+ | |||
+ | The configuration is made via an [http://www.ovt.com/download_document.php?type=document&DID=63 OmniVision Serial Camera Control Bus] | ||
+ | (OSCCB), | ||
+ | which greatly corresponds to an I2C interface. | ||
+ | |||
+ | The write address is 42<sub>h</sub>, the read address 43<sub>h</sub>. | ||
+ | |||
+ | === References === | ||
+ | A [http://hamsterworks.co.nz/mediawiki/index.php/OV7670_camera VHDL design example] provides a good understanding of the camera system. | ||
+ | |||
+ | == Photonfocus == | ||
+ | |||
+ | Foreseen: OEM-D1024E-160-LC, RS232 control | ||
+ | |||
+ | [[File:Camera Photonfocus.jpg|center|500px]] | ||
[[Category:Hardware]] | [[Category:Hardware]] | ||
[[Category:Cubesat]] | [[Category:Cubesat]] | ||
[[Category:Gumstix]] | [[Category:Gumstix]] |
Latest revision as of 11:00, 9 December 2015
|
Connector
The connector layout is:
connector pin |
signal | FPGA pin |
function |
---|---|---|---|
1 | 3.3 V | power supply | |
2 | GND | ||
3 | TxD / SCLK | A4 | RS232 / I2C control |
4 | RxD / SDA | B10 | |
5 | Frame valid / VSync | A5 | frame control |
6 | Line valid / HRef | C5 | |
7 | Data valid | B6 | |
8 | Pixel clock | A10 | |
9 | D0 | A6 | frame data |
10 | D1 | D6 | |
11 | D2 | A7 | |
12 | D3 | C6 | |
13 | D4 | B8 | |
14 | D5 | C7 | |
15 | D6 | A8 | |
16 | D7 | D8 | |
17 | D8 | A9 | |
18 | D9 | C8 | |
19 | D10 | A13 | |
20 | D11 | C9 | |
21 | CC1 / ExtSync | A14 | camera control |
22 | CC2 / XCLK | C14 | |
23 | CC3 / Reset | B14 | |
24 | CC4 / PowerDn | D14 |
Camera modules
The connector is meant for use with different camera modules.
OV7670
The OV7670 camera module has:
- selectable resolutions comprising VGA, CIF and their subsizes
- 16 bit RGB, YUV or Bayer raw data
- an I2C control interface
Timing generation
The camera module receives a master clock signal: XCLK
.
This clock signal can be multiplied by 1, 4, 6 or 8 by a PLL (DBLV[7:6] at 6Bh).
The resulting frequency can be divided by an even number ( 2*(CLKRC[5:0]+1), set at 11h ).
This provides the reference clock for the image acquisition.
The acquired image can be downsampled by a factor of 2, 4 or 8 (SCALING_PCLK_DIV[3:0] at 73h). After this, a digital zoom out can be applied with a factor of 1 to 2 separately in the horizontal (REG74[6:0] at 74h) and vertical (REG75[6:0] at 75h) directions. These operations can be enabled or disabled (COM3[3:2] at 0Ch).
From these, the video control signals are generated:
-
VSYNC
: vertical sync. with programmable polarity -
HREF
: enable signal for reading, with programmable polarity -
PCLK
: pixel clock
Configuration
The configuration is made via an OmniVision Serial Camera Control Bus (OSCCB), which greatly corresponds to an I2C interface.
The write address is 42h, the read address 43h.
References
A VHDL design example provides a good understanding of the camera system.
Photonfocus
Foreseen: OEM-D1024E-160-LC, RS232 control