Languages/SystemVerilog/Syntax
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reg [7:0] r1 [1:256]; // [7:0] packed, [1:256] unpacked | reg [7:0] r1 [1:256]; // [7:0] packed, [1:256] unpacked | ||
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+ | |||
+ | == Operators == | ||
+ | === Equality == | ||
+ | Operands are compared bit by bit, with zero filling if the two operands do not have the same length. | ||
+ | The result is 0 (false) or 1 (true). | ||
+ | There are two types of Equality operators. | ||
+ | |||
+ | ==== Logical Equality ==== | ||
+ | The result is x, if either operand contains an x or a z. | ||
+ | {| class=wikitable | ||
+ | |- | ||
+ | |'''Operator'''||'''Description | ||
+ | |- | ||
+ | |a == b ||a equal to b, result may be unknown (logical equality) | ||
+ | |- | ||
+ | |a != b ||a not equal to b, result may be unknown (logical equality) | ||
+ | |||
+ | ==== Case Equality ==== | ||
+ | Bits with x and z are included in the comparison and must match for the result to be true. | ||
+ | {| class=wikitable | ||
+ | |- | ||
+ | |'''Operator'''||'''Description | ||
+ | |- | ||
+ | |a === b ||a equal to b, including x and z (Case equality) | ||
+ | |- | ||
+ | |a !== b ||a not equal to b, including x and z (Case inequality) | ||
== Escape sequences for format specifications == | == Escape sequences for format specifications == |
Revision as of 12:16, 12 November 2013
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Integer data types
Type | States | Language | Size [bits] | |
shortint | 2 | SystemVerilog | 16 | signed integer |
int | 2 | SystemVerilog | 32 | signed integer |
longint | 2 | SystemVerilog | 64 | signed integer |
byte | 2 | SystemVerilog | 8 | signed integer or ASCII character |
bit | 2 | SystemVerilog | user-defined (default 1 bit) | |
logic | 4 | SystemVerilog | user-defined (default 1 bit) | |
reg | 4 | Verilog-2001 | user-defined (default 1 bit) | |
integer | 4 | Verilog-2001 | 32 | signed integer |
time | 4 | Verilog-2001 | 64 | unsigned integer |
The 4-state data types can have unknown (X) and high-impedance (Z) values. When a 4-state value is cast to a 2-state value, X and Z are converted to 0. When X and Z are not needed, use the 2-state types (int, bit), which execute faster.
Arrays
packed array
The dimensions declared before the object name (vector width) are called packed array.
bit [7:0] c1;
unpacked array
The dimensions declared after the object name (array size) are called unpacked array.
real u [7:0];
mixed
Mixed versions are also used (array of registers).
reg [7:0] r1 [1:256]; // [7:0] packed, [1:256] unpacked
Operators
= Equality
Operands are compared bit by bit, with zero filling if the two operands do not have the same length. The result is 0 (false) or 1 (true). There are two types of Equality operators.
Logical Equality
The result is x, if either operand contains an x or a z.
Operator | Description | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
a == b | a equal to b, result may be unknown (logical equality) | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
a != b | a not equal to b, result may be unknown (logical equality)
Case EqualityBits with x and z are included in the comparison and must match for the result to be true.
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