Languages
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* [[Languages/SystemVerilog_libraries|System Verilog Libraries]] | * [[Languages/SystemVerilog_libraries|System Verilog Libraries]] | ||
* [[Languages/SystemVerilog_links|System Verilog Links]] | * [[Languages/SystemVerilog_links|System Verilog Links]] | ||
− | * [[Languages/ | + | * [[Languages/UVM_definition|Universal Verification Methodology]] |
− | * [[Languages/ | + | * [[Languages/UVM_links|Universal Verification Methodology Links]] |
== Perl == | == Perl == |
Revision as of 15:33, 9 February 2012
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Knowledge Database about Languages used in the field of Digital Hardware Designing
VHDL
Tcl_Tk
SystemVerilog
- System Verilog Syntax
- System Verilog Libraries
- System Verilog Links
- Universal Verification Methodology
- Universal Verification Methodology Links