Hardware/Mezzanine/Ethertap
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| − | == | + | == Ethernet Tap == |
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| + | The Ethernet tap allows to monitor the traffic on an Ethernet link, filter the frames and send them to the Ethernet connector on the main FPGA board. | ||
| + | For this purpose, a specific design has to be loaded into the main FPGA. | ||
| + | |||
| + | General purpose I/O signals on 2 Header connectors enable to debug FPGA designs. | ||
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{|class=wikitable | {|class=wikitable | ||
|- | |- | ||
| − | ! | + | ! Version || Photo || Schematic || Description |
|- | |- | ||
| V1.0 || [[File:FPGA_Mezza_Ethernettap.jpg|200px|Ethernettap Mezzanine]] || [[Media:FPGA_Mezza_Ethernettap_schematic.pdf|FPGA Ethernettap Mezza Schematic PDF]] || 2 Port Ethernet Active Tap with divers Debug Headers | | V1.0 || [[File:FPGA_Mezza_Ethernettap.jpg|200px|Ethernettap Mezzanine]] || [[Media:FPGA_Mezza_Ethernettap_schematic.pdf|FPGA Ethernettap Mezza Schematic PDF]] || 2 Port Ethernet Active Tap with divers Debug Headers | ||
| − | |||
|} | |} | ||
| + | |||
| + | Check for availability in the hardware [[Hardware/Stock_Mez#EthernetTap_Mezzanine|Stock]]. | ||
[[Category:Hardware]][[Category:Mezzanine]] | [[Category:Hardware]][[Category:Mezzanine]] | ||
Revision as of 16:53, 2 November 2012
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Ethernet Tap
The Ethernet tap allows to monitor the traffic on an Ethernet link, filter the frames and send them to the Ethernet connector on the main FPGA board. For this purpose, a specific design has to be loaded into the main FPGA.
General purpose I/O signals on 2 Header connectors enable to debug FPGA designs.
| Version | Photo | Schematic | Description |
|---|---|---|---|
| V1.0 |  |
FPGA Ethernettap Mezza Schematic PDF | 2 Port Ethernet Active Tap with divers Debug Headers |
Check for availability in the hardware Stock.
