Projects/CubeCluster
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The CubeCluster unit deals with a multiprocessor architecture based on Intel Edison SoCs which can reduce the consumption significally. On the the second hand, a FPGA acts as master device onboard for the data acquisition and data IO routing. The FPGA focuses on scheduling of the data treatements which are parallelized on each Intel Edison SoC. | The CubeCluster unit deals with a multiprocessor architecture based on Intel Edison SoCs which can reduce the consumption significally. On the the second hand, a FPGA acts as master device onboard for the data acquisition and data IO routing. The FPGA focuses on scheduling of the data treatements which are parallelized on each Intel Edison SoC. | ||
| − | [[File:Intel_edison_reduced.png|200px | + | [[File:Intel_edison_reduced.png|200px|Intel Edison System]] |
| − | [[File:Igloo.png|200px | + | [[File:Igloo.png|200px|Intel Edison System]] |
= Further Infos = | = Further Infos = | ||
[[Projects/CubeCluster/Demonstrator|Demonstrator]] | [[Projects/CubeCluster/Demonstrator|Demonstrator]] | ||
Revision as of 10:01, 5 October 2015
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CubeCluster Project
CubeCluster is a development project part for the pico-satellite CubeSat. It is an low-power high-performance image processing board unit for CubeSat, allowing a high speed data treatment and low power consumption.
The CubeCluster unit deals with a multiprocessor architecture based on Intel Edison SoCs which can reduce the consumption significally. On the the second hand, a FPGA acts as master device onboard for the data acquisition and data IO routing. The FPGA focuses on scheduling of the data treatements which are parallelized on each Intel Edison SoC.
