Projects/usbCypress/VHDL Summary

From UIT

Revision as of 11:55, 11 June 2012 by Zas (Talk | contribs)

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

Jump to: navigation, search

make an interface: Slave FIFO

make an part command, a part data receive and a part data send.

It's possible to work in synchronous or asynchronous mode. To know follow max speed of USB, we work in synchronous mode.

Retrieved from "https://wiki.hevs.ch/uit/index.php5?title=Projects/usbCypress/VHDL_Summary&oldid=1144"

Personal tools

Log in

Browse

Toolbox