The Ethernet tap allows to monitor the traffic on an Ethernet link, filter the frames and send them to the Ethernet connector on the main FPGA board. For this purpose, a specific design has to be loaded into the main FPGA.
General purpose I/O signals on 2 Header connectors enable to debug FPGA designs.
|V1.0||FPGA Ethernettap Mezza Schematic PDF||2 Port Ethernet Active Tap with divers Debug Headers|
Check for availability in the hardware stock.
This Hardware can simply used as an active Ethernet measurement point to intercept an Ethernet communication and filter out certain packages.
More information and the VHDL program can be found in the Component page: EthernetTap