Hardware/FPGAEBS
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! Type || FPGA-EBS Full board || FPGA-EBS Student board || FPGA-EBS Mezzanine || Schematic || UCF || Description | ! Type || FPGA-EBS Full board || FPGA-EBS Student board || FPGA-EBS Mezzanine || Schematic || UCF || Description | ||
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− | | V2.1 || [[File:FPGA_Full_v2_1.jpg|200px|FPGA EBS V2.1]] [[Hardware/Stock_FPGA#Full|boards 30-35]] || [[File:FPGA_Student_v2_1.jpg|200px|FPGA EBS Student Version V2.1]] [[Hardware/Stock_FPGA#Student|boards 11-13]]|| [[File:FPGA_Mezza_v2_1.jpg|115px|FPGA EBS Mezza V2.1]] [[Hardware/Stock_FPGA#Mezzanine|boards 40-41]] || [[Media:FPGA_EBS_v2_1_schematics.pdf|FPGA-EBS v2.1 Schematic PDF]] || FPGA EBS v2 UCF Files <br> [[Media:FPGA_EBS_v2_xc3s1200e.ucf|XC3S1200e]] <br> [[Media:FPGA_EBS_v2_xc3s500e.ucf|XC3S500e]] || Improved second version of FPGA-EBS comes with Xilinx XC3S500e or XC3S1200E. Note that there is a different UCF Pin constraining file | + | | V2.1 || [[File:FPGA_Full_v2_1.jpg|200px|FPGA EBS V2.1]] [[Hardware/Stock_FPGA#Full|boards 30-35]] || [[File:FPGA_Student_v2_1.jpg|200px|FPGA EBS Student Version V2.1]] [[Hardware/Stock_FPGA#Student|boards 11-13]]|| [[File:FPGA_Mezza_v2_1.jpg|115px|FPGA EBS Mezza V2.1]] [[Hardware/Stock_FPGA#Mezzanine|boards 40-41]] || [[Media:FPGA_EBS_v2_1_schematics.pdf|FPGA-EBS v2.1 Schematic PDF]] || FPGA EBS v2 UCF Files <br> [[Media:FPGA_EBS_v2_xc3s1200e.ucf|XC3S1200e]] <br> [[Media:FPGA_EBS_v2_xc3s500e.ucf|XC3S500e]] || Improved second version of FPGA-EBS comes with a Xilinx ''XC3S500e'' or a ''XC3S1200E''. Note that there is a different UCF Pin constraining file depending on the FPGA type. Furthermore there is a ''xcf04s'' Xilinx Platform Flash for persistent configuration |
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| V2.0 || [[File:FPGA_Full_v2_0.jpg|200px|FPGA EBS V2.0]] [[Hardware/Stock_FPGA#Full_2|boards 21-28]] || [[File:FPGA_Student_v2_0.jpg|200px|FPGA EBS Student Version V2.0]] [[Hardware/Stock_FPGA#Student_2|boards 1-8]] || Not existing ||[[Media:FPGA_EBS_v2_0_schematics.pdf|FPGA-EBS v2.0 Schematic PDF]] || FPGA EBS v2 UCF Files <br> [[Media:FPGA_EBS_v2_xc3s1200e.ucf|XC3S1200e]] <br> [[Media:FPGA_EBS_v2_xc3s500e.ucf|XC3S500e]] || Second FPGA-EBS Version comes only with Xilinx XC3S500E | | V2.0 || [[File:FPGA_Full_v2_0.jpg|200px|FPGA EBS V2.0]] [[Hardware/Stock_FPGA#Full_2|boards 21-28]] || [[File:FPGA_Student_v2_0.jpg|200px|FPGA EBS Student Version V2.0]] [[Hardware/Stock_FPGA#Student_2|boards 1-8]] || Not existing ||[[Media:FPGA_EBS_v2_0_schematics.pdf|FPGA-EBS v2.0 Schematic PDF]] || FPGA EBS v2 UCF Files <br> [[Media:FPGA_EBS_v2_xc3s1200e.ucf|XC3S1200e]] <br> [[Media:FPGA_EBS_v2_xc3s500e.ucf|XC3S500e]] || Second FPGA-EBS Version comes only with Xilinx XC3S500E |
Revision as of 15:58, 4 March 2013
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A short description of the FPGA-EBS board is found on the ISI Project Page.
Board families
There are several versions of FPGA EBS Boards. The stock can be verified and updated on-line.
Type | FPGA-EBS Full board | FPGA-EBS Student board | FPGA-EBS Mezzanine | Schematic | UCF | Description |
---|---|---|---|---|---|---|
V2.1 | boards 30-35 | boards 11-13 | boards 40-41 | FPGA-EBS v2.1 Schematic PDF | FPGA EBS v2 UCF Files XC3S1200e XC3S500e |
Improved second version of FPGA-EBS comes with a Xilinx XC3S500e or a XC3S1200E. Note that there is a different UCF Pin constraining file depending on the FPGA type. Furthermore there is a xcf04s Xilinx Platform Flash for persistent configuration |
V2.0 | boards 21-28 | boards 1-8 | Not existing | FPGA-EBS v2.0 Schematic PDF | FPGA EBS v2 UCF Files XC3S1200e XC3S500e |
Second FPGA-EBS Version comes only with Xilinx XC3S500E |
V1.0 | FPGA-EBS v1.0 Schematic PDF | Not available | First FPGA-EBS Version comes with a Xilinx XC2S150 or XC2S250 FPGA. Please note that for Spartan 2 is no longer supported by Xilinx, an ISE Version <= 9.2i has to be used |
A VHDL test code with the default UCF Files can be found at the EDA SVN Reopsitory
UCF Pin Differences
On the FPGA-EBS v2.X Boards, you can find two different FPGA Spartan3 Chips.
There are 3 Pin differences between Boards with XC3S500E and XC3S1200E.
Pin Function | Pin on XC3S500E | Pin on XC3S1200E |
---|---|---|
ParallelPort2(16) | F4 | E6 |
MezzanineData(9) | E17 | E3 |
sdCke | P15 | E4 |
Other changes between FPGA-EBS V2.0 and V2.1
There are some other changes made in the Ethernet part of those boards. Several bugs were changes and corrected.
- TCT and RCT Pins of the Ethernetconnector were strapped to 3.3V, and decoupled with Capacitors (C59 & C104)
- Serial Capacitors on the RX+ and RX- lines were replaced by 0Ohm Resistors (R61 & R63)
- Proper Reset circuit for the Ethernetphy is put on place (D13, D14, R62 & C108)