Libero IDE presentation

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Contents

Libero IDE is used to program the Microchip FPGAs.

Work environment

At HEI, we laucnch Libero IDE directly from HDL Designer. The setup bases on a set of environment variables.

Files

The main design files are located in $PATH/Board/concat:

$DESIGN.vhd
$DESIGN.pdc

The Physical Design Constraints .pdc file specifies the I/O locations and electric levels.

Further design files are found in $PATH/Board/Libero:

$DESIGN.prjx
synthesis/$DESIGN_syn.prj
designer/impl1/$DESIGN.adb
designer/impl1/$DESIGN.ide_des
designer/impl1/$DESIGN.pdb

This second set of files is copied into a temporary directory which will be additionally populated by the numerous design files generated by the deign tool.

Tasks

Launching the tools is done in two steps.

  • with the top-level block selected, the prepare for synthesis task does the following:
    • the design tool generates a single VHDL file
    • the trimLibs.pl script replaces all library definitions with the one of work
  • the Libero Project Navigator task does the following:
    • the Update prjx.pl script updates the paths specified in the .prjx file to reflect the project location's.
    • the Libero IDE is launched

Interactive run of the Libero tools

To check the synthesis and downnload results wit a better accuracy, one can start Libero IDE and go through:

  • Synthesize -> open interactively
    • implementation option -> specify clock frequency
    • run
    • view log
  • Compile -> open interactively
    • I/O Attibute Editor
    • Layout
    • Programming File
  • FlashPro -> open interactively
    • verify programmer
    • verify .pdb bitstream file
    • program

Tips

PDC

To ensure the correct behavior of the project, specify ALL I/Os in your .pdc file.

If the following window is shown when trying to configure the FPGA, stop there as one pin has been omitted and it may create undefined and unwanted problems :

Libero PDC warning

Clocks

Only one clock should be found during the synthesize.

More than one will also create undefined behaviors. It can be seen in the $DESIGN.srr file, under the Clock Summary. Such, the real behavior will not reflect the simulation.

For example, in the following, a second clock is found in the block setting the coils signals:

Libero Inferred clocks

For the record, the coils were then wrongly set, making the stepper slip and consume a lot of current.

Optimizations

Libero will optimize cloned functionalities, remove unnecessary registers ...

It may happen that a whole route is removed (e.g. in the students solutions, where the distancePulse is not used by default). If the signal is kept in the PDC, you may encounter an error that it is not found because Libero removed it internally.

To avoid those problems, open the symbol of the Kart_Board block in HDL, then on the right click on Declarations.

There, it is possible to specify pre-defined attributes that will impact the synthesis. To keep all signals, the following is used :

Libero Attributes

Configuring the FPGA

After the bitfile is generated by Libero, one must flash it on the FPGA.

FlashPro

In libero, a right-click on Program Device-> open interactively will open the FlashPro software.

It will automatically load the .pdb file (bitstream for the FPGA) and, if the programmer is already connected, will list it under Programmer Name :

FlashPro
  • A bitstream file can be loaded through Configuration -> Load programming file.
  • A programmer can be detected by clicking Refresh/Rescan for Programmers

You have to connect both the USB-C cable (for power) and the FlashPro dongle on the FPGA daughterboard to flash it if the card is not inserted into a powered motherboard. Otherwise, the FlashPro dongle is sufficient.

Then, simply click on the Program button to flash the FPGA.

OpenOCD

Flashing the FPGA by using the USB-C cable only is possible using OpenOCD, the daughterboard being plugged into a powered motherboard or not.

Dialog-warning.png

Developer here : this method, while proven to work, is not the recommended one yet nor are your teachers trained on it and thus YOU WON'T GET HELP FROM THEM !

Use it only if you are confident enough in your skills to follow a tutorial, use command lines tools, tweak your machine and debug random problems you may encounter on the way !

Setup environment

  • First, download OpenOCD unofficial binary releases for your platform, or build it yourself
    • Once built / installed / unpacked, you must add the folder containing the openocd program (e.g. on Windows, the bin folder) to your path
    • If done correctly, opening a terminal and typing openocd -v should output the OpenOCD version
  • On the side, download the required files for the FPGA to be supported
  • Copy the board, interface and support folders into your OpenOCD folder (on Windows, under share/openocd/scripts/; on Mac, under scripts/)

For Windows users, an extra step is required for OpenOCD to detect the board:

  • In the support folder, run zadig, select the USB <-> Serial Converter (Interface 0) and push Replace Driver (admin rights required)
  • Without it, OpenOCD WON'T detect the FPGA
Zadig

Generate programming files

  • Open FlashPro from Libero as before (or open it and load the .pdb file)
  • Click on File -> Export -> Export Single Device SVF File and select the desired output folder

Prepare the board

Flash the board

  • Open a terminal inside the folder where the files have been generated
  • Type and launch the following command : openocd -f target/igloo_agln250.cfg -c init -c "svf -quiet Kart_Board_ERASE.svf" -c "svf -quiet Kart_Board_PROGRAM.svf" -c "svf -quiet Kart_Board_VERIFY.svf" -c shutdown
    • You should see the following two lines logged:
      • Info : clock speed 4000 kHz
      • Info : JTAG tap: agl250.tap tap/device found: 0x1ba541cf (mfg: 0x0e7 (GateField), part: 0xba54, ver: 0x1)
    • While the board is programmed, only the erase, program and verify steps are logged (you can remove the -quiet switch to see which command is actually processed, but with more than a million for the program part, it only slows down the process)
  • Once the three steps are completed (around 4 minutes), your design is ready to be challenged !
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