Libero IDE presentation
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== Tips == | == Tips == | ||
+ | === PDC === | ||
To ensure the correct behavior of the project, specify '''ALL''' I/Os in your '''.pdc''' file. | To ensure the correct behavior of the project, specify '''ALL''' I/Os in your '''.pdc''' file. | ||
Line 60: | Line 61: | ||
[[File:libero_pdc_warning.png|70%|center|Libero PDC warning]] | [[File:libero_pdc_warning.png|70%|center|Libero PDC warning]] | ||
− | For example, | + | === Clocks === |
+ | Only one clock should be found during the synthesize. | ||
+ | |||
+ | More than one will also create undefined behaviors. It can be seen in the '''$DESIGN.srr''' file, under the '''Clock Summary'''. | ||
+ | Such, the real behavior will not reflect the simulation. | ||
+ | |||
+ | For example, in the following, a second clock is found in the block setting the coils signals: | ||
+ | [[File:libero_multiclocks.png|70%|center|Libero Inferred clocks]] | ||
+ | |||
+ | ''For the record, the coils were then wrongly set, making the stepper slip and consume a lot of current.'' | ||
+ | |||
+ | === Optimizations === | ||
+ | Libero will optimize cloned functionalities, remove unnecessary registers ... | ||
+ | |||
+ | It may happen that a whole route is removed (e.g. in the students solutions, where the '''distancePulse''' is not used by default). | ||
+ | If the signal is kept in the PDC, you may encounter an error that it is not found because Libero removed it internally. | ||
+ | |||
+ | To avoid those problems, open the '''symbol''' of the '''Kart_Board''' block in HDL, then on the right click on '''Declarations'''. | ||
+ | |||
+ | There, it is possible to specify pre-defined attributes that will impact the synthesis. To keep all signals, the following is used : | ||
+ | [[File:libero_attributes.png|20%|center|Libero Attributes]] | ||
+ | |||
+ | = Configuring the FPGA = | ||
+ | After the bitfile is generated by Libero, one must flash it on the FPGA. | ||
+ | |||
+ | == FlashPro == | ||
+ | In libero, a right-click on '''Program Device-> open interactively''' will open the '''FlashPro''' software. | ||
+ | |||
+ | It will automatically load the '''.pdb''' file (bitstream for the FPGA) and, if the programmer is already connected, will list it under '''Programmer Name''' : | ||
+ | [[File:kart_flashpro.png|550px|center|FlashPro]] | ||
+ | |||
+ | * A bitstream file can be loaded through '''Configuration''' -> '''Load programming file'''. | ||
+ | * A programmer can be detected by clicking '''Refresh/Rescan for Programmers''' | ||
+ | |||
+ | You have to connect both the '''USB-C''' cable (for power) and the '''FlashPro dongle''' on the [[Kart/Daughterboard|FPGA daughterboard]] to flash it if the card is not inserted into a powered [[Kart/Motherboard|motherboard]]. | ||
+ | Otherwise, the '''FlashPro dongle''' is sufficient. | ||
+ | |||
+ | Then, simply click on the '''Program''' button to flash the FPGA. | ||
+ | |||
+ | == OpenOCD == | ||
+ | Flashing the FPGA by using the '''USB-C''' cable only is possible using [https://openocd.org/ OpenOCD], the [[Kart/Daughterboard|daughterboard]] being plugged into a powered [[Kart/Motherboard|motherboard]] or not. | ||
+ | {{WarningBox|content= | ||
+ | '''Developer here : this method, while proven to work, is not the recommended one yet nor are your teachers trained on it and thus YOU WON'T GET HELP FROM THEM ! | ||
+ | |||
+ | Use it only if you are confident enough in your skills to follow a tutorial, use command lines tools, tweak your machine and debug random problems you may encounter on the way !''' | ||
+ | }} | ||
+ | |||
+ | === Setup environment === | ||
+ | First, download [https://github.com/xpack-dev-tools/openocd-xpack/releases/ OpenOCD unofficial binary releases] for your platform, or [https://sourceforge.net/p/openocd/code/ci/master/tree/ build it yourself]. | ||
+ | |||
+ | ==== On Windows ==== | ||
+ | * Once built / installed / unpacked, you must add the folder containing the '''openocd''' program (e.g. on Windows, the <code>bin</code> folder) to your '''path''' | ||
+ | ** If done correctly, opening a terminal and typing <code>openocd -v</code> should output the OpenOCD version | ||
+ | * On the side, download the [[Media:AGLN250_OpenOCDSupport.zip| required files]] for the FPGA to be supported | ||
+ | * Copy the '''board''', '''interface''' and '''support''' folders into your OpenOCD folder (on Windows, under <code>share/openocd/scripts/</code>; on Mac, under <code>scripts/</code>) | ||
+ | |||
+ | For '''Windows''' users, an extra step is required for '''OpenOCD''' to detect the board: | ||
+ | * In the '''support''' folder, run '''zadig''', select the '''USB <-> Serial Converter (Interface 0)''' (may also be named '''EBS3_Igloo_Serial (Interface 0)''') and push '''Replace Driver''' (admin rights required) | ||
+ | * ''Without it, '''OpenOCD''' WON'T detect the FPGA'' | ||
+ | [[File:Kart_zadig.jpg|450px|center|Zadig]] | ||
+ | |||
+ | ==== On Linux ==== | ||
+ | |||
+ | Download [https://github.com/xpack-dev-tools/openocd-xpack/releases OpenOCD xpack] to <code>/usr/opt/OpenOCD</code>: | ||
+ | DOWNLOAD_URL='https://github.com/xpack-dev-tools/openocd-xpack/releases/download' | ||
+ | VERSION='0.11.0-5' | ||
+ | curl -L $DOWNLOAD_URL/v$VERSION/xpack-openocd-$VERSION-linux-x64.tar.gz -o /tmp/openocd.tar.gz | ||
+ | mkdir /tmp/OpenOCD | ||
+ | tar -xvzpf /tmp/openocd.tar.gz -C /tmp/OpenOCD/ | ||
+ | sudo mv /tmp/OpenOCD/xpack-openocd-* /usr/opt/OpenOCD | ||
+ | /usr/opt/OpenOCD/bin/openocd -v | ||
+ | |||
+ | Add usb rule for FTDI chip: | ||
+ | lsusb | grep FT2232C | ||
+ | cat /usr/opt/OpenOCD/contrib/60-openocd.rules | grep -A 1 FT2232 | ||
+ | sudo cp /usr/opt/OpenOCD/contrib/60-openocd.rules /etc/udev/rules.d/ | ||
+ | sudo reboot | ||
+ | |||
+ | Download EBS3 zip from <code>https://gitlab.hevs.ch/infrastructure/labos/digital-electronics/boards/ebs3</code>, and extract the definition files: | ||
+ | unzip ~/Downloads/ebs3-master.zip -d /tmp | ||
+ | sudo cp -pv /tmp/ebs3-master/21_OpenOCD/target/*.cfg /usr/opt/OpenOCD/scripts/target/ | ||
+ | sudo cp -pv /tmp/ebs3-master/21_OpenOCD/interface/*.cfg /usr/opt/OpenOCD/scripts/interface/ | ||
+ | |||
+ | === Generate programming files === | ||
+ | * Open FlashPro from Libero as before (or open it and load the '''.pdb''' file) | ||
+ | * Click on <code>File -> Export -> Export Single Device SVF File</code> and select the desired output folder | ||
+ | |||
+ | === Prepare the board === | ||
+ | * Plug the [[Kart/Daughterboard|daughterboard]] through a '''USB-C''' cable | ||
+ | |||
+ | === Flash the board === | ||
+ | ==== On Windows ==== | ||
+ | * Open a terminal inside the folder where the files have been generated | ||
+ | * Type and launch the following command : <code>openocd -f target/igloo_agln250.cfg -c init -c "svf -quiet Kart_Board_ERASE.svf" -c "svf -quiet Kart_Board_PROGRAM.svf" -c "svf -quiet Kart_Board_VERIFY.svf" -c shutdown</code> | ||
+ | ** You should see the following two lines logged: | ||
+ | ***'''Info : clock speed 4000 kHz''' | ||
+ | ***'''Info : JTAG tap: agl250.tap tap/device found: 0x1ba541cf (mfg: 0x0e7 (GateField), part: 0xba54, ver: 0x1)''' | ||
+ | ** While the board is programmed, only the '''erase, program''' and '''verify''' steps are logged (you can remove the '''-quiet''' switch to see which command is actually processed, but with more than a million for the program part, it only slows down the process) | ||
+ | * Once the three steps are completed (around 4 minutes), your design is ready to be challenged ! | ||
+ | |||
+ | ==== On Linux ==== | ||
+ | |||
+ | Flash the FPGA: | ||
+ | OPEN_OCD_DIR='/usr/opt/OpenOCD/bin' | ||
+ | OPEN_OCD_FILES_DIR='/home/francois/Favorites/ElN_local/ElN_kart/Board/oocd' | ||
+ | OPEN_OCD_FILE='agl600_test' | ||
+ | $OPEN_OCD_DIR/openocd \ | ||
+ | -f target/igloo_agl600.cfg \ | ||
+ | -c init \ | ||
+ | -c "svf -quiet $OPEN_OCD_FILES_DIR/${OPEN_OCD_FILE}_ERASE.svf" \ | ||
+ | -c "svf -quiet $OPEN_OCD_FILES_DIR/${OPEN_OCD_FILE}_PROGRAM.svf" \ | ||
+ | -c "svf -quiet $OPEN_OCD_FILES_DIR/${OPEN_OCD_FILE}_VERIFY.svf" \ | ||
+ | -c shutdown |
Latest revision as of 13:16, 7 July 2023
|
Libero IDE is used to program the Microchip FPGAs.
Work environment
At HEI, we laucnch Libero IDE directly from HDL Designer. The setup bases on a set of environment variables.
Files
The main design files are located in $PATH/Board/concat
:
$DESIGN.vhd $DESIGN.pdc
The Physical Design Constraints .pdc
file specifies the I/O locations and electric levels.
Further design files are found in $PATH/Board/Libero
:
$DESIGN.prjx synthesis/$DESIGN_syn.prj designer/impl1/$DESIGN.adb designer/impl1/$DESIGN.ide_des designer/impl1/$DESIGN.pdb
This second set of files is copied into a temporary directory which will be additionally populated by the numerous design files generated by the deign tool.
Tasks
Launching the tools is done in two steps.
- with the top-level block selected, the
prepare for synthesis
task does the following:- the design tool generates a single VHDL file
- the
trimLibs.pl
script replaces all library definitions with the one ofwork
- the
Libero Project Navigator
task does the following:- the
Update prjx.pl
script updates the paths specified in the.prjx
file to reflect the project location's. - the Libero IDE is launched
- the
Interactive run of the Libero tools
To check the synthesis and downnload results wit a better accuracy, one can start Libero IDE and go through:
- Synthesize -> open interactively
- implementation option -> specify clock frequency
- run
- view log
- Compile -> open interactively
- I/O Attibute Editor
- Layout
- Programming File
- FlashPro -> open interactively
- verify programmer
- verify
.pdb
bitstream file - program
Tips
PDC
To ensure the correct behavior of the project, specify ALL I/Os in your .pdc file.
If the following window is shown when trying to configure the FPGA, stop there as one pin has been omitted and it may create undefined and unwanted problems :
Clocks
Only one clock should be found during the synthesize.
More than one will also create undefined behaviors. It can be seen in the $DESIGN.srr file, under the Clock Summary. Such, the real behavior will not reflect the simulation.
For example, in the following, a second clock is found in the block setting the coils signals:
For the record, the coils were then wrongly set, making the stepper slip and consume a lot of current.
Optimizations
Libero will optimize cloned functionalities, remove unnecessary registers ...
It may happen that a whole route is removed (e.g. in the students solutions, where the distancePulse is not used by default). If the signal is kept in the PDC, you may encounter an error that it is not found because Libero removed it internally.
To avoid those problems, open the symbol of the Kart_Board block in HDL, then on the right click on Declarations.
There, it is possible to specify pre-defined attributes that will impact the synthesis. To keep all signals, the following is used :
Configuring the FPGA
After the bitfile is generated by Libero, one must flash it on the FPGA.
FlashPro
In libero, a right-click on Program Device-> open interactively will open the FlashPro software.
It will automatically load the .pdb file (bitstream for the FPGA) and, if the programmer is already connected, will list it under Programmer Name :
- A bitstream file can be loaded through Configuration -> Load programming file.
- A programmer can be detected by clicking Refresh/Rescan for Programmers
You have to connect both the USB-C cable (for power) and the FlashPro dongle on the FPGA daughterboard to flash it if the card is not inserted into a powered motherboard. Otherwise, the FlashPro dongle is sufficient.
Then, simply click on the Program button to flash the FPGA.
OpenOCD
Flashing the FPGA by using the USB-C cable only is possible using OpenOCD, the daughterboard being plugged into a powered motherboard or not.
Developer here : this method, while proven to work, is not the recommended one yet nor are your teachers trained on it and thus YOU WON'T GET HELP FROM THEM !
Use it only if you are confident enough in your skills to follow a tutorial, use command lines tools, tweak your machine and debug random problems you may encounter on the way !
Setup environment
First, download OpenOCD unofficial binary releases for your platform, or build it yourself.
On Windows
- Once built / installed / unpacked, you must add the folder containing the openocd program (e.g. on Windows, the
bin
folder) to your path- If done correctly, opening a terminal and typing
openocd -v
should output the OpenOCD version
- If done correctly, opening a terminal and typing
- On the side, download the required files for the FPGA to be supported
- Copy the board, interface and support folders into your OpenOCD folder (on Windows, under
share/openocd/scripts/
; on Mac, underscripts/
)
For Windows users, an extra step is required for OpenOCD to detect the board:
- In the support folder, run zadig, select the USB <-> Serial Converter (Interface 0) (may also be named EBS3_Igloo_Serial (Interface 0)) and push Replace Driver (admin rights required)
- Without it, OpenOCD WON'T detect the FPGA
On Linux
Download OpenOCD xpack to /usr/opt/OpenOCD
:
DOWNLOAD_URL='https://github.com/xpack-dev-tools/openocd-xpack/releases/download' VERSION='0.11.0-5' curl -L $DOWNLOAD_URL/v$VERSION/xpack-openocd-$VERSION-linux-x64.tar.gz -o /tmp/openocd.tar.gz mkdir /tmp/OpenOCD tar -xvzpf /tmp/openocd.tar.gz -C /tmp/OpenOCD/ sudo mv /tmp/OpenOCD/xpack-openocd-* /usr/opt/OpenOCD /usr/opt/OpenOCD/bin/openocd -v
Add usb rule for FTDI chip:
lsusb | grep FT2232C cat /usr/opt/OpenOCD/contrib/60-openocd.rules | grep -A 1 FT2232 sudo cp /usr/opt/OpenOCD/contrib/60-openocd.rules /etc/udev/rules.d/ sudo reboot
Download EBS3 zip from https://gitlab.hevs.ch/infrastructure/labos/digital-electronics/boards/ebs3
, and extract the definition files:
unzip ~/Downloads/ebs3-master.zip -d /tmp sudo cp -pv /tmp/ebs3-master/21_OpenOCD/target/*.cfg /usr/opt/OpenOCD/scripts/target/ sudo cp -pv /tmp/ebs3-master/21_OpenOCD/interface/*.cfg /usr/opt/OpenOCD/scripts/interface/
Generate programming files
- Open FlashPro from Libero as before (or open it and load the .pdb file)
- Click on
File -> Export -> Export Single Device SVF File
and select the desired output folder
Prepare the board
- Plug the daughterboard through a USB-C cable
Flash the board
On Windows
- Open a terminal inside the folder where the files have been generated
- Type and launch the following command :
openocd -f target/igloo_agln250.cfg -c init -c "svf -quiet Kart_Board_ERASE.svf" -c "svf -quiet Kart_Board_PROGRAM.svf" -c "svf -quiet Kart_Board_VERIFY.svf" -c shutdown
- You should see the following two lines logged:
- Info : clock speed 4000 kHz
- Info : JTAG tap: agl250.tap tap/device found: 0x1ba541cf (mfg: 0x0e7 (GateField), part: 0xba54, ver: 0x1)
- While the board is programmed, only the erase, program and verify steps are logged (you can remove the -quiet switch to see which command is actually processed, but with more than a million for the program part, it only slows down the process)
- You should see the following two lines logged:
- Once the three steps are completed (around 4 minutes), your design is ready to be challenged !
On Linux
Flash the FPGA:
OPEN_OCD_DIR='/usr/opt/OpenOCD/bin' OPEN_OCD_FILES_DIR='/home/francois/Favorites/ElN_local/ElN_kart/Board/oocd' OPEN_OCD_FILE='agl600_test' $OPEN_OCD_DIR/openocd \ -f target/igloo_agl600.cfg \ -c init \ -c "svf -quiet $OPEN_OCD_FILES_DIR/${OPEN_OCD_FILE}_ERASE.svf" \ -c "svf -quiet $OPEN_OCD_FILES_DIR/${OPEN_OCD_FILE}_PROGRAM.svf" \ -c "svf -quiet $OPEN_OCD_FILES_DIR/${OPEN_OCD_FILE}_VERIFY.svf" \ -c shutdown