Libero IDE presentation
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Revision as of 17:28, 21 December 2020 by Francois.corthay (Talk | contribs)
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Libero IDE is used to program the Microchip FPGAs.
Work environment
At HEI, we laucnch Libero IDE directly from HDL Designer.
Files
The main design files are located in $PATH/Board/concat
:
$DESIGN.vhd $DESIGN.pdc
The Physical Design Constraints .pdc
file specifies the I/O locations and electric levels.
Further design files are found in $PATH/Board/Libero
:
$DESIGN.prjx synthesis/$DESIGN_syn.prj designer/impl1/$DESIGN.adb designer/impl1/$DESIGN.ide_des designer/impl1/$DESIGN.pdb
This second set of files is copied into a temporary directory which will be additionally populated by the numerous design files generated by the deign tool.
Tasks
Launching the tools is done in two steps.
- with the top-level block selected, the
prepare for synthesis
task does the following:- the design tool generates a single VHDL file
- the
trimLibs.pl
script replaces all library definitions with the one ofwork
- the
Libero Project Navigator
task does the following:- the
Update prjx.pl
script updates the paths specified in the.prjx
file to reflect the project location's. - the Libero IDE is launched
- the
Interactive run of the Libero tools
To check the synthesis and downnload results wit a better accuracy, one can start Libero IDE and go through:
- Synthesize -> open interactively
- implementation option -> specify clock frequency
- run
- view log
- Compile -> open interactively
- I/O Attibute Editor
- Layout
- Programming File
- FlashPro -> open interactively
- verify programmer
- verify
.pdb
bitstream file - program