Components/IP/Ethernet

These IPs can be found on the EDA Repository: svn: https://repos.hevs.ch/svn/eda/

There are 2 ISI Ethernet IP systems:

• the light core with ARP and UDP/IP capabilities
• the full core with additional ICMP (for ping) and DHCP support

Both designs come in 3 blocks:

• a MII to dual port RAM interface
• a protocol decoder which retrieves the payload from the complete frame
• the application part where the user places one block for each function (protocol) to implement

Testbench

For both designs testbenches are given. They allow to send predefined packets to the Ethernet cores and record and save the packets sent by the Ethernet cores to a human readable text file. The test benches are based on the MII receiver and the MII sender.