Tools/Xilinx ISE/UCF ShortGuide

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A short guide to constraints in FPGA

by Pierre-Andre Mudry 2011

This small guide indicates how to resolve most timing problems / constraints inside an FPGA. In fact, most problems with an FPGA timing occur because of three reasons:

  1. False paths
  2. Timing issues due to reading data from outside the FPGA with a clock
  3. Timing issues due to outputting data to another component from the FPGA with a clock.

1. Problem A : false paths

A simple example for the first case is when you generate the TX line of an UART or when you consider interrupt lines in a uBlaze (for instance). In both cases, those signals are not synchronous with respect to your clock. You must then indicate that those nets are to be ignored by timing checks. In order to do it, for Xilinx FPGA you must use the TIG constraint (which stands for Timing IGnore). The only problem here is that you can't put that constraint in your VHDL file but you have to put it in the UCF file. When you have internal signals, you require to use the complete path of the net (which can be found for example by displaying the schematic of your design or with the report of the timing analyser).

An example of such a constraint for a UCF file is given here :

INST "broadenc_cpu_i/axi_intc_0/axi_intc_0/INTC_CORE_I/hw_intr_1" TNM = UBlaze_Interrupts;
INST "broadenc_cpu_i/axi_intc_0/axi_intc_0/INTC_CORE_I/hw_intr_2" TNM = UBlaze_Interrupts;
TIMESPEC TS_UBlaze_Interrupts = TO "UBlaze_Interrupts" TIG; # We don't care of timing for interrupts

This creates a group for two signals and then use the TIG constraint to it. If your instance name is incorrect, the synthesis tool will complaint.

2. Problem B : reading data from outside the FPGA

When you read synchronous data (i.e. with an incoming clock) in an FPGA, you must be sure that you respect setup and hold times in your input register. In order to do, a simple constraint like

OFFSET = IN 4 ns VALID 8 ns BEFORE "mb_vclk";

indicate that the data that are registered with the signal mb_vclk (which must be a constrained clock) must comply with a setup of 4 ns and a hold time of 4 ns. By doing it like this, you won't have any problem with source synchronous systems (in which the clock are transmitted from another device with the data).

3. Problem C: outputting synchronous data correctly with an FPGA

When you generate data for another system in your FPGA and you also generate the clock for that system ( a global clock is not shared between all elements of the system (FPGA and device) for that bus), making sure that the data are aligned with the clock and are output with correct setup and hold times consist in putting the following constraint :

net "ve_vclk" TNM_NET = "vdata_out";
net "ve_vy<0>" TNM_NET = "vdata_out";
net "ve_vy<1>" TNM_NET = "vdata_out";
net "ve_vy<2>" TNM_NET = "vdata_out";
net "ve_vy<3>" TNM_NET = "vdata_out";
net "ve_vy<4>" TNM_NET = "vdata_out";
TIMEGRP "vdata_out" OFFSET = OUT AFTER "mb_vclk" REFERENCE_PIN "ve_vclk";

Those constraints have the following meaning : we group all the signals in a group "vdata_out". This group is generated with a clock (here mb_vclk, which remains inside the FPGA) and the clock for the whole group (which is output and constitues the reference for all the other signals) is ve_vclk. Note that this pin must be included in the group.

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