Standards/Ethernet PTP/DP83640
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=== Registers === | === Registers === | ||
− | There are 20 fixed registers (0x00 ... 0x13) and 7 pages with 12 registers (0x14 ... 0x1F) each. In the fixed register PAGESEL (address: 0x13) field PAGE_SEL (bits: 2:0) | + | There are 20 fixed registers (0x00 ... 0x13) and 7 pages with 12 registers (0x14 ... 0x1F) each. In the fixed register PAGESEL (address: 0x13) field PAGE_SEL (bits: 2:0) selects the page to access. The pages are: |
− | + | ; Page 0 : Extended Registers | |
− | : Extended Registers | + | ; Page 1 |
− | + | ||
: Test Registers - Reserved | : Test Registers - Reserved | ||
− | + | ; Page 2 | |
: Link Diagnostics Registers | : Link Diagnostics Registers | ||
− | + | ; Page 3 | |
: Reserved Registers - Reserved | : Reserved Registers - Reserved | ||
− | + | ; Page 4 | |
: PTP 1588 Base Registers | : PTP 1588 Base Registers | ||
− | + | ; Page 5 | |
: PTP 1588 Configuration Registers | : PTP 1588 Configuration Registers | ||
− | + | ; Page 6 | |
: PTP 1588 Configuration Registers | : PTP 1588 Configuration Registers | ||
=== RS232 access === | === RS232 access === | ||
− | |||
− | |||
− | |||
− | |||
− | + | The information below shows how the access to the phyter is implemented in our [[Projects#PTP|PTP projects]]. | |
− | + | Nevertheless there is information that might be useful for other projects related to the DP83640 phyter, like the different access sequences. | |
− | write - phy no. - reg. no - | + | The baud rate configured in PTP is 9600. |
− | + | ==== Command Syntax ==== | |
+ | |||
+ | Each command consists of 2 or 3 parameters. As there are more than one device on the FPGA accessible by RS232, we have to select the PTP phyter at first. | ||
+ | {|class=wikitable | ||
+ | |+ RS232 MII access | ||
+ | |- | ||
+ | ! action !! command | ||
+ | |- | ||
+ | | enable mii || <code><span style="color:red">miim0 y</span></code> | ||
+ | |} | ||
+ | <code>miim0</code> specifies that we like to access to the first MIIM interface, in our case this is the one of the PTP phyter. With the parameter <code>y</code> it is selected on, whereas <code>n</code> would deselect it. | ||
+ | Then we can write or read the registers. | ||
+ | {|class=wikitable | ||
+ | |+ RS232 register access | ||
+ | ! action !! command | ||
+ | |- | ||
+ | | read - phy no. - reg. no || <code><span style="color:red">rd 0113 01</span></code> | ||
+ | |- | ||
+ | | write - phy no. - reg. no - data || <code><span style="color:red">wr 0113 0004</span></code> | ||
+ | |} | ||
+ | The first parameter <code>rd</code> or <code>wr</code> selects the access direction. This is followed by <code>01</code> and the address of the register <code>13</code> in hexadecimal. The last parameter depends on the access direction. For read accesses its the number of consecutive read accesses to be done <code>01</code>. For write accesses its the data to be written to the register, again in hexadecimal format <code>0004</code>. | ||
+ | |||
+ | Each access returns a value on the RS232 link. For write accesses its the data parameter that is looped back. This does not imply, that the value is really written to the register. For read accesses naturally the value read from the register is returned. | ||
+ | |||
+ | ==== Base access ==== | ||
+ | |||
+ | {|class=wikitable | ||
+ | |- | ||
+ | |+ RS232 base access | ||
+ | |- | ||
+ | ! action !! command | ||
+ | |- | ||
+ | | enable mii || <code><span style="color:red">miim0 y</span></code> | ||
+ | |- | ||
+ | | read - phy no. - reg. no || <code><span style="color:red">rd 0113 01</span></code> | ||
+ | |- | ||
+ | | write - phy no. - reg. no - data || <code><span style="color:red">wr 0113 0004</span></code> | ||
+ | |- | ||
+ | |} | ||
==== Select page ==== | ==== Select page ==== | ||
− | + | {|class=wikitable | |
− | + | |- | |
− | + | |+ RS232 select page | |
− | + | |- | |
− | + | ! action !! command !! response | |
+ | |- | ||
+ | | Select Page 4 || <code><span style="color:red">wr 0113 0004</span></code> | ||
+ | |- | ||
+ | | Read selected page || <code><span style="color:red">rd 0113 01</span></code> || <code><span style="color:blue">0004</span></code> | ||
+ | |- | ||
+ | |} | ||
==== Init phyter ==== | ==== Init phyter ==== | ||
− | Select Page 4 | + | |
− | + | {|class=wikitable | |
− | Enable Clock | + | |- |
− | + | |+ RS232 init phyter | |
− | Select Page 5 | + | |- |
− | + | ! action !! command | |
− | Configure TX: SYNC_1STEP | + | |- |
− | + | | Select Page 4 || <code><span style="color:red">wr 0113 0004</span></code> | |
+ | |- | ||
+ | | Enable Clock || <code><span style="color:red">wr 0114 0004</span></code> | ||
+ | |- | ||
+ | | Select Page 5 || <code><span style="color:red">wr 0113 0005</span></code> | ||
+ | |- | ||
+ | | Configure TX: | ||
+ | *SYNC_1STEP | ||
+ | *DR_INSERT | ||
+ | *IGNORE_2STEP | ||
+ | *CRC_1STEP | ||
+ | *CHK_1STEP | ||
+ | *TX_L2_EN | ||
+ | *TX_IPV4_EN | ||
+ | *TX_PTP_VER | ||
+ | *TX_TS_EN | ||
+ | || <code><span style="color:red">wr 0116 AEA5</span></code> | ||
+ | |- | ||
+ | |} | ||
==== Time ==== | ==== Time ==== | ||
===== Set ===== | ===== Set ===== | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | ===== Read ===== | + | {|class=wikitable |
− | Select Page 4 | + | |- |
− | + | |+ RS232 set time | |
− | Write to PTP_CTL with the PTP_Rd_Clk bit set | + | |- |
− | + | ! action !! command | |
− | Read Clock_time_ns[15:0] from PTP_TDR | + | |- |
− | + | | Select Page 4 || <code><span style="color:red">wr 0113 0004</span></code> | |
− | + | |- | |
− | Read Clock_time_ns[31:16] from PTP_TDR | + | | Write Clock_time_ns[15:0] to PTP_TDR || <code><span style="color:red">wr 0115 0000</span></code> |
− | + | |- | |
− | + | | Write Clock_time_ns[31:16] to PTP_TDR || <code><span style="color:red">wr 0115 0000</span></code> | |
− | Read Clock_time_sec[15:0] from PTP_TDR | + | |- |
− | + | | Write Clock_time_sec[15:0] to PTP_TDR || <code><span style="color:red">wr 0115 0000</span></code> | |
− | + | |- | |
− | Read Clock_time_sec[31:16] from PTP_TDR | + | | Write Clock_time_sec[31:16] to PTP_TDR || <code><span style="color:red">wr 0115 0000</span></code> |
− | + | |- | |
− | <span style="color:blue"> | + | | Write to PTP_CTL with the PTP_Load_Clk bit set || <code><span style="color:red">wr 0114 0010</span></code> |
+ | |- | ||
+ | |} | ||
+ | |||
+ | ===== Read ===== | ||
+ | |||
+ | {|class=wikitable | ||
+ | |- | ||
+ | |+ RS232 read time | ||
+ | |- | ||
+ | ! action !! command !! response | ||
+ | |- | ||
+ | | Select Page 4 || <code><span style="color:red">wr 0113 0004</span></code> | ||
+ | |- | ||
+ | | Write to PTP_CTL with the PTP_Rd_Clk bit set || <code><span style="color:red">TBD</span></code> | ||
+ | |- | ||
+ | | Read Clock_time_ns[15:0] from PTP_TDR || <code><span style="color:red">rd 0115 01</span></code> || <code><span style="color:blue">4878</span></code> | ||
+ | |- | ||
+ | | Read Clock_time_ns[31:16] from PTP_TDR || <code><span style="color:red">rd 0115 01</span></code> || <code><span style="color:blue">055D</span></code> | ||
+ | |- | ||
+ | | Read Clock_time_sec[15:0] from PTP_TDR || <code><span style="color:red">rd 0115 01</span></code> || <code><span style="color:blue">0DFF</span></code> | ||
+ | |- | ||
+ | | Read Clock_time_sec[31:16] from PTP_TDR || <code><span style="color:red">rd 0115 01</span></code> || <code><span style="color:blue">0000</span></code> | ||
+ | |- | ||
+ | |} | ||
+ | |||
+ | ==== Event ==== | ||
+ | |||
+ | ===== Set ===== | ||
+ | {|class=wikitable | ||
+ | |- | ||
+ | |+ RS232 timestamp GPIO | ||
+ | |- | ||
+ | ! action !! command | ||
+ | |- | ||
+ | | Select Page 5 || <code><span style="color:red">wr 0113 0005</span></code> | ||
+ | |- | ||
+ | | Config PTP_EVNT: | ||
+ | * EVNT_RISE | ||
+ | * EVNT_GPIO 1 | ||
+ | * EVNT_SEL 1 | ||
+ | * EVNT_WR 1 | ||
+ | "0100_0001_0000_0011" | ||
+ | || <code><span style="color:red">wr 0115 4103</span></code> | ||
+ | |- | ||
+ | |} | ||
+ | |||
+ | ===== Read ===== | ||
+ | {|class=wikitable | ||
+ | |- | ||
+ | |+ RS232 timestamp GPIO | ||
+ | |- | ||
+ | ! action !! command !! response | ||
+ | |- | ||
+ | | Select Page 4 || <code><span style="color:red">wr 0113 0004</span></code> | ||
+ | |- | ||
+ | | Read PTP_ESTS || <code><span style="color:red">rd 011E 01</span></code> || <code><span style="color:blue">00E5 00A5 07A5</span></code> | ||
+ | |- | ||
+ | | Read PTP_EDATA || <code><span style="color:red">rd 011F 01</span></code> || <code><span style="color:blue">0370 31F9 0557</span></code> | ||
+ | |- | ||
+ | |} | ||
== References == | == References == |
Latest revision as of 08:48, 11 July 2014
|
The National Semiconductor DP83640 Precision PHYTER is an ethernet transceiver that integrates certain features useful for the implementation of the IEEE 1588 standard. The three main features are:
- packet time stamping
- synchronised clock generation
(PTP_COC and PTP_RATE register)
- event triggering and time stamping with GPIOs
other technical features include:
- IEEE 1588 V1 and V2 support
- Timestamp resolution of 8 ns (Allows sub 10 ns synchronization to master reference)
- Error-free Operation up to 150 meters CAT5 cable
IEEE 1588
Paket Timestamp
TX
Outgoing IEEE 1588 V1 and V2 Event messages are detected automatically and a timestamp is recorded. For the two-step mode an interrupt can be generated when a timestamp is ready to be read by the PHYTER controller. For the one-step mode the transmitter can also be configured to insert the timestamp directly into Sync messages.
RX
Incoming IEEE 1588 V1 and V2 Event messages are detected automatically and a timestamp is recorded. An interrupt is generated an the timestamp can be read by the PHYTER controller. The timestamp can also be integrated into the received packet for easy transmission to the PHYTER controller.
Event
Output Trigger
A trigger signal based on the IEEE 1588 time value can be put out a desired GPIO. The triggers can generate:
- one-time rising or falling edge
- single pulse with a configurable with
- periodic signal
The device supports up to 8 triggers. They can be put out on single GPIOs or be OR'ed together on single GPIOs.
Input Timestamp
The Event Timestamp Unit can monitor up to 8 events of:
- rising edge
- falling edge
- both
assigned to any of the GPIOs. Event timestamps should be adjusted by 35 ns to compensate for internal delays.
MII
PHY address
The PHY address can be configured with 5 pins. The default setting is 00001. With all bits tied to 0 the PHY enters Isolation Mode where it disables parts of the MII interface.
Broadcast mode
The device is configured to accept broadcast messages by setting a register bit (PHY_CR2: BC_WRITE).
Registers
There are 20 fixed registers (0x00 ... 0x13) and 7 pages with 12 registers (0x14 ... 0x1F) each. In the fixed register PAGESEL (address: 0x13) field PAGE_SEL (bits: 2:0) selects the page to access. The pages are:
- Page 0
- Extended Registers
- Page 1
- Test Registers - Reserved
- Page 2
- Link Diagnostics Registers
- Page 3
- Reserved Registers - Reserved
- Page 4
- PTP 1588 Base Registers
- Page 5
- PTP 1588 Configuration Registers
- Page 6
- PTP 1588 Configuration Registers
RS232 access
The information below shows how the access to the phyter is implemented in our PTP projects. Nevertheless there is information that might be useful for other projects related to the DP83640 phyter, like the different access sequences.
The baud rate configured in PTP is 9600.
Command Syntax
Each command consists of 2 or 3 parameters. As there are more than one device on the FPGA accessible by RS232, we have to select the PTP phyter at first.
action | command |
---|---|
enable mii | miim0 y
|
miim0
specifies that we like to access to the first MIIM interface, in our case this is the one of the PTP phyter. With the parameter y
it is selected on, whereas n
would deselect it.
Then we can write or read the registers.
action | command |
---|---|
read - phy no. - reg. no | rd 0113 01
|
write - phy no. - reg. no - data | wr 0113 0004
|
The first parameter rd
or wr
selects the access direction. This is followed by 01
and the address of the register 13
in hexadecimal. The last parameter depends on the access direction. For read accesses its the number of consecutive read accesses to be done 01
. For write accesses its the data to be written to the register, again in hexadecimal format 0004
.
Each access returns a value on the RS232 link. For write accesses its the data parameter that is looped back. This does not imply, that the value is really written to the register. For read accesses naturally the value read from the register is returned.
Base access
action | command |
---|---|
enable mii | miim0 y
|
read - phy no. - reg. no | rd 0113 01
|
write - phy no. - reg. no - data | wr 0113 0004
|
Select page
action | command | response |
---|---|---|
Select Page 4 | wr 0113 0004
| |
Read selected page | rd 0113 01 |
0004
|
Init phyter
action | command |
---|---|
Select Page 4 | wr 0113 0004
|
Enable Clock | wr 0114 0004
|
Select Page 5 | wr 0113 0005
|
Configure TX:
|
wr 0116 AEA5
|
Time
Set
action | command |
---|---|
Select Page 4 | wr 0113 0004
|
Write Clock_time_ns[15:0] to PTP_TDR | wr 0115 0000
|
Write Clock_time_ns[31:16] to PTP_TDR | wr 0115 0000
|
Write Clock_time_sec[15:0] to PTP_TDR | wr 0115 0000
|
Write Clock_time_sec[31:16] to PTP_TDR | wr 0115 0000
|
Write to PTP_CTL with the PTP_Load_Clk bit set | wr 0114 0010
|
Read
action | command | response |
---|---|---|
Select Page 4 | wr 0113 0004
| |
Write to PTP_CTL with the PTP_Rd_Clk bit set | TBD
| |
Read Clock_time_ns[15:0] from PTP_TDR | rd 0115 01 |
4878
|
Read Clock_time_ns[31:16] from PTP_TDR | rd 0115 01 |
055D
|
Read Clock_time_sec[15:0] from PTP_TDR | rd 0115 01 |
0DFF
|
Read Clock_time_sec[31:16] from PTP_TDR | rd 0115 01 |
0000
|
Event
Set
action | command |
---|---|
Select Page 5 | wr 0113 0005
|
Config PTP_EVNT:
"0100_0001_0000_0011" |
wr 0115 4103
|
Read
action | command | response |
---|---|---|
Select Page 4 | wr 0113 0004
| |
Read PTP_ESTS | rd 011E 01 |
00E5 00A5 07A5
|
Read PTP_EDATA | rd 011F 01 |
0370 31F9 0557
|