Tools/Xilinx ISE/ISE Libraries
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For this, a simulator like [[Tools/Mentor_Modelsim|Mentor Modelsim]] or [[Tools/Mentor_Questasim|Mentor Questasim]] has to be installed on the system. | For this, a simulator like [[Tools/Mentor_Modelsim|Mentor Modelsim]] or [[Tools/Mentor_Questasim|Mentor Questasim]] has to be installed on the system. | ||
− | These libraries can be linked as ''downstream only'' libraries with a '' | + | These libraries can be linked as ''downstream only'' libraries with a ''ModelSim'' mapping in [[Tools/Mentor_HDL_Designer|Mentor HDL Designer]] or directly be mapped inside the simulator. |
=== Running the tool === | === Running the tool === |
Revision as of 17:28, 21 January 2014
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Compiling Simulation Libraries
To be able to simulate Xilinx IPs or netlists, one or more of the simulation libraries
- simprim
- unisim
- secureip
- xilinxcorelib
- edk
might be needed. These libraries can be compiled with a tool provided with ISE.
For this, a simulator like Mentor Modelsim or Mentor Questasim has to be installed on the system.
These libraries can be linked as downstream only libraries with a ModelSim mapping in Mentor HDL Designer or directly be mapped inside the simulator.
Running the tool
There are different ways to launch the tool:
- When you are using XPS as stand-alone (not launched from ISE), the tool can be launched in the menu Simulation => Compiling Simulation Libraries.
- On Windows the command Simulation Library Compilation Wizard can be found in the Start menu Start => Xilinx ISE Design Suite XX.X => ISE Design Tools =>
- On Linux the command compxlib can be executed in the console.
Each chapter below corresponds to window in the GUI.
Selecting a Simulator
On the first window a simulator has to be chosen. Verify that the Simulator Executable Location matches the simulator you like to use.
Selecting HDL
The second window serves to select the simulation language. VHDL is a good choice.
Select Device Families
Here the supported device families can be chosen. Be aware that choosing many families increases the needed hard-disk space as well as the compilation time significantly.
Select libraries for Functional and Timing Simulation
Choose the libraries regarding your needs. The selection may influence hard-disk space as well as the compilation time significantly.
Output directory
For the further explanation the default path ISE/<language>/<simulator>/<version>/<platform>
is used.
Compiling
During the compile process, a console like window is shown with information about the current actions. Please be patient. At the end a Compilation Summary is shown.
Compilation Summary
The same Compilation Summary as above is shown again in a more graphical way. If all went well the error count should be 0.
Effective Location
The libraries unisim, simprim and xilinxcorelib can be found at the location specified in the Output directory above:
e.g. ISE/vhdl/questa/10.0b/lin64/unisim
The library secureip is only existing in Verilog in will be placed always under this language, independent of the HDL language chosen above:
e.g. ISE/verilog/questa/10.0b/lin64/secureip
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