Tools/Xilinx ISE/DCM
From UIT
Revision as of 16:22, 10 August 2015 by Francois.corthay (Talk | contribs)
|
In order to divide the clock frequency, a Digital Clock manager (DCM) module can be instantiated.
Instantiation
Saprtan 3
In a Spartan-3 FPGA, the associated module is a DCM_SP
.
Here a sample code:
library UNISIM; use UNISIM.vcomponents.all; I_DCM: dcm_clkgen generic map ( clkfx_multiply => 3, clkfx_divide => 8, clkin_period => 10.0 ) port map ( rst => '0', clkin => clockIn, clkfx => clock );
The library
definition and its associated use
clause must:
- be in the code for compilation
- be commented-out for HDL Designer to generate the concatenated file (else further simulation VHDL code is included and will not be accepted at synthesis)
- be de-commented for synthesis (which is done in our
trimlibs.pl
)
Additionally, the hdp
preferences file must specify a definition in the HDS section for the unisim library:
[ModelSim] unisim = $ISE_HOME/ISE/vhdl/unisim/work [hdl] unisim = $ISE_HOME/../../vhdl/src/unisims [hds] unisim = $HDS_PROJECT_DIR/../unisim/hds
If it isn't the case, the HDL Designer vhdl file generator will produce:
Error: Cross reference directory '' cannot be written to. Generation cannot proceed. Please make sure this directory is write enabled.
Saprtan 6
In a Spartan-6 FPGA, the associated module is a DCM_SP
or a DCM_CLKGEN
.
Here a sample code:
library UNISIM; use UNISIM.vcomponents.all; I_DCM: dcm_clkgen generic map ( clkfx_multiply => 3, clkfx_divide => 8, clkin_period => 10.0 ) port map ( rst => '0', freezedcm => '0', clkin => clockIn, clkfx => clock );
UniSim library
Adding the UniSim to the HDS tool can be done with:
unisim = $ISE_HOME/ISE/vhdl/src/unisims
Navigation
Tools/Xilinx_ISE/ISE_Libraries
Tools/Xilinx_ISE
Tools/Xilinx_ISE/UCF_Timing_Constraints